1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn302_init.h"
27 #include "dcn302_resource.h"
28 #include "dcn302_dccg.h"
29 #include "irq/dcn302/irq_service_dcn302.h"
30
31 #include "dcn30/dcn30_dio_link_encoder.h"
32 #include "dcn30/dcn30_dio_stream_encoder.h"
33 #include "dcn30/dcn30_dwb.h"
34 #include "dcn30/dcn30_dpp.h"
35 #include "dcn30/dcn30_hubbub.h"
36 #include "dcn30/dcn30_hubp.h"
37 #include "dcn30/dcn30_mmhubbub.h"
38 #include "dcn30/dcn30_mpc.h"
39 #include "dcn30/dcn30_opp.h"
40 #include "dcn30/dcn30_optc.h"
41 #include "dcn30/dcn30_resource.h"
42
43 #include "dcn20/dcn20_dsc.h"
44 #include "dcn20/dcn20_resource.h"
45
46 #include "dml/dcn30/dcn30_fpu.h"
47
48 #include "dcn10/dcn10_resource.h"
49
50 #include "dce/dce_abm.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_aux.h"
53 #include "dce/dce_clock_source.h"
54 #include "dce/dce_hwseq.h"
55 #include "dce/dce_i2c_hw.h"
56 #include "dce/dce_panel_cntl.h"
57 #include "dce/dmub_abm.h"
58 #include "dce/dmub_psr.h"
59 #include "clk_mgr.h"
60
61 #include "hw_sequencer_private.h"
62 #include "reg_helper.h"
63 #include "resource.h"
64 #include "vm_helper.h"
65
66 #include "dml/dcn302/dcn302_fpu.h"
67
68 #include "dimgrey_cavefish_ip_offset.h"
69 #include "dcn/dcn_3_0_2_offset.h"
70 #include "dcn/dcn_3_0_2_sh_mask.h"
71 #include "dpcs/dpcs_3_0_0_offset.h"
72 #include "dpcs/dpcs_3_0_0_sh_mask.h"
73 #include "nbio/nbio_7_4_offset.h"
74 #include "amdgpu_socbb.h"
75
76 #define DC_LOGGER_INIT(logger)
77
78 static const struct dc_debug_options debug_defaults_drv = {
79 .disable_dmcu = true,
80 .force_abm_enable = false,
81 .timing_trace = false,
82 .clock_trace = true,
83 .disable_pplib_clock_request = true,
84 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
85 .force_single_disp_pipe_split = false,
86 .disable_dcc = DCC_ENABLE,
87 .vsr_support = true,
88 .performance_trace = false,
89 .max_downscale_src_width = 7680,/*upto 8K*/
90 .disable_pplib_wm_range = false,
91 .scl_reset_length10 = true,
92 .sanity_checks = false,
93 .underflow_assert_delay_us = 0xFFFFFFFF,
94 .dwb_fi_phase = -1, // -1 = disable,
95 .dmub_command_table = true,
96 .use_max_lb = true
97 };
98
99 static const struct dc_debug_options debug_defaults_diags = {
100 .disable_dmcu = true,
101 .force_abm_enable = false,
102 .timing_trace = true,
103 .clock_trace = true,
104 .disable_dpp_power_gate = true,
105 .disable_hubp_power_gate = true,
106 .disable_clock_gate = true,
107 .disable_pplib_clock_request = true,
108 .disable_pplib_wm_range = true,
109 .disable_stutter = false,
110 .scl_reset_length10 = true,
111 .dwb_fi_phase = -1, // -1 = disable
112 .dmub_command_table = true,
113 .enable_tri_buf = true,
114 .disable_psr = true,
115 .use_max_lb = true
116 };
117
118 enum dcn302_clk_src_array_id {
119 DCN302_CLK_SRC_PLL0,
120 DCN302_CLK_SRC_PLL1,
121 DCN302_CLK_SRC_PLL2,
122 DCN302_CLK_SRC_PLL3,
123 DCN302_CLK_SRC_PLL4,
124 DCN302_CLK_SRC_TOTAL
125 };
126
127 static const struct resource_caps res_cap_dcn302 = {
128 .num_timing_generator = 5,
129 .num_opp = 5,
130 .num_video_plane = 5,
131 .num_audio = 5,
132 .num_stream_encoder = 5,
133 .num_dwb = 1,
134 .num_ddc = 5,
135 .num_vmid = 16,
136 .num_mpc_3dlut = 2,
137 .num_dsc = 5,
138 };
139
140 static const struct dc_plane_cap plane_cap = {
141 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
142 .blends_with_above = true,
143 .blends_with_below = true,
144 .per_pixel_alpha = true,
145 .pixel_format_support = {
146 .argb8888 = true,
147 .nv12 = true,
148 .fp16 = true,
149 .p010 = true,
150 .ayuv = false,
151 },
152 .max_upscale_factor = {
153 .argb8888 = 16000,
154 .nv12 = 16000,
155 .fp16 = 16000
156 },
157 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
158 .max_downscale_factor = {
159 .argb8888 = 167,
160 .nv12 = 167,
161 .fp16 = 167
162 },
163 16,
164 16
165 };
166
167 /* NBIO */
168 #define NBIO_BASE_INNER(seg) \
169 NBIO_BASE__INST0_SEG ## seg
170
171 #define NBIO_BASE(seg) \
172 NBIO_BASE_INNER(seg)
173
174 #define NBIO_SR(reg_name)\
175 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
176 mm ## reg_name
177
178 /* DCN */
179 #undef BASE_INNER
180 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
181
182 #define BASE(seg) BASE_INNER(seg)
183
184 #define SR(reg_name)\
185 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
186
187 #define SF(reg_name, field_name, post_fix)\
188 .field_name = reg_name ## __ ## field_name ## post_fix
189
190 #define SRI(reg_name, block, id)\
191 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
192
193 #define SRI2(reg_name, block, id)\
194 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
195
196 #define SRII(reg_name, block, id)\
197 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
198 mm ## block ## id ## _ ## reg_name
199
200 #define DCCG_SRII(reg_name, block, id)\
201 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
202 mm ## block ## id ## _ ## reg_name
203
204 #define VUPDATE_SRII(reg_name, block, id)\
205 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
206 mm ## reg_name ## _ ## block ## id
207
208 #define SRII_DWB(reg_name, temp_name, block, id)\
209 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
210 mm ## block ## id ## _ ## temp_name
211
212 #define SRII_MPC_RMU(reg_name, block, id)\
213 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
214 mm ## block ## id ## _ ## reg_name
215
216 static const struct dcn_hubbub_registers hubbub_reg = {
217 HUBBUB_REG_LIST_DCN30(0)
218 };
219
220 static const struct dcn_hubbub_shift hubbub_shift = {
221 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
222 };
223
224 static const struct dcn_hubbub_mask hubbub_mask = {
225 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
226 };
227
228 #define vmid_regs(id)\
229 [id] = { DCN20_VMID_REG_LIST(id) }
230
231 static const struct dcn_vmid_registers vmid_regs[] = {
232 vmid_regs(0),
233 vmid_regs(1),
234 vmid_regs(2),
235 vmid_regs(3),
236 vmid_regs(4),
237 vmid_regs(5),
238 vmid_regs(6),
239 vmid_regs(7),
240 vmid_regs(8),
241 vmid_regs(9),
242 vmid_regs(10),
243 vmid_regs(11),
244 vmid_regs(12),
245 vmid_regs(13),
246 vmid_regs(14),
247 vmid_regs(15)
248 };
249
250 static const struct dcn20_vmid_shift vmid_shifts = {
251 DCN20_VMID_MASK_SH_LIST(__SHIFT)
252 };
253
254 static const struct dcn20_vmid_mask vmid_masks = {
255 DCN20_VMID_MASK_SH_LIST(_MASK)
256 };
257
dcn302_hubbub_create(struct dc_context * ctx)258 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
259 {
260 int i;
261
262 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
263
264 if (!hubbub3)
265 return NULL;
266
267 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
268
269 for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
270 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
271
272 vmid->ctx = ctx;
273
274 vmid->regs = &vmid_regs[i];
275 vmid->shifts = &vmid_shifts;
276 vmid->masks = &vmid_masks;
277 }
278
279 return &hubbub3->base;
280 }
281
282 #define vpg_regs(id)\
283 [id] = { VPG_DCN3_REG_LIST(id) }
284
285 static const struct dcn30_vpg_registers vpg_regs[] = {
286 vpg_regs(0),
287 vpg_regs(1),
288 vpg_regs(2),
289 vpg_regs(3),
290 vpg_regs(4),
291 vpg_regs(5)
292 };
293
294 static const struct dcn30_vpg_shift vpg_shift = {
295 DCN3_VPG_MASK_SH_LIST(__SHIFT)
296 };
297
298 static const struct dcn30_vpg_mask vpg_mask = {
299 DCN3_VPG_MASK_SH_LIST(_MASK)
300 };
301
dcn302_vpg_create(struct dc_context * ctx,uint32_t inst)302 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
303 {
304 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
305
306 if (!vpg3)
307 return NULL;
308
309 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
310
311 return &vpg3->base;
312 }
313
314 #define afmt_regs(id)\
315 [id] = { AFMT_DCN3_REG_LIST(id) }
316
317 static const struct dcn30_afmt_registers afmt_regs[] = {
318 afmt_regs(0),
319 afmt_regs(1),
320 afmt_regs(2),
321 afmt_regs(3),
322 afmt_regs(4),
323 afmt_regs(5)
324 };
325
326 static const struct dcn30_afmt_shift afmt_shift = {
327 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
328 };
329
330 static const struct dcn30_afmt_mask afmt_mask = {
331 DCN3_AFMT_MASK_SH_LIST(_MASK)
332 };
333
dcn302_afmt_create(struct dc_context * ctx,uint32_t inst)334 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
335 {
336 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
337
338 if (!afmt3)
339 return NULL;
340
341 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
342
343 return &afmt3->base;
344 }
345
346 #define audio_regs(id)\
347 [id] = { AUD_COMMON_REG_LIST(id) }
348
349 static const struct dce_audio_registers audio_regs[] = {
350 audio_regs(0),
351 audio_regs(1),
352 audio_regs(2),
353 audio_regs(3),
354 audio_regs(4),
355 audio_regs(5),
356 audio_regs(6)
357 };
358
359 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
360 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
361 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
362 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
363
364 static const struct dce_audio_shift audio_shift = {
365 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
366 };
367
368 static const struct dce_audio_mask audio_mask = {
369 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
370 };
371
dcn302_create_audio(struct dc_context * ctx,unsigned int inst)372 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
373 {
374 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
375 }
376
377 #define stream_enc_regs(id)\
378 [id] = { SE_DCN3_REG_LIST(id) }
379
380 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
381 stream_enc_regs(0),
382 stream_enc_regs(1),
383 stream_enc_regs(2),
384 stream_enc_regs(3),
385 stream_enc_regs(4)
386 };
387
388 static const struct dcn10_stream_encoder_shift se_shift = {
389 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
390 };
391
392 static const struct dcn10_stream_encoder_mask se_mask = {
393 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
394 };
395
dcn302_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)396 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
397 {
398 struct dcn10_stream_encoder *enc1;
399 struct vpg *vpg;
400 struct afmt *afmt;
401 int vpg_inst;
402 int afmt_inst;
403
404 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
405 if (eng_id <= ENGINE_ID_DIGE) {
406 vpg_inst = eng_id;
407 afmt_inst = eng_id;
408 } else
409 return NULL;
410
411 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
412 vpg = dcn302_vpg_create(ctx, vpg_inst);
413 afmt = dcn302_afmt_create(ctx, afmt_inst);
414
415 if (!enc1 || !vpg || !afmt) {
416 kfree(enc1);
417 kfree(vpg);
418 kfree(afmt);
419 return NULL;
420 }
421
422 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
423 &se_shift, &se_mask);
424
425 return &enc1->base;
426 }
427
428 #define clk_src_regs(index, pllid)\
429 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
430
431 static const struct dce110_clk_src_regs clk_src_regs[] = {
432 clk_src_regs(0, A),
433 clk_src_regs(1, B),
434 clk_src_regs(2, C),
435 clk_src_regs(3, D),
436 clk_src_regs(4, E)
437 };
438
439 static const struct dce110_clk_src_shift cs_shift = {
440 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
441 };
442
443 static const struct dce110_clk_src_mask cs_mask = {
444 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
445 };
446
dcn302_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)447 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
448 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
449 {
450 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
451
452 if (!clk_src)
453 return NULL;
454
455 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
456 clk_src->base.dp_clk_src = dp_clk_src;
457 return &clk_src->base;
458 }
459
460 BREAK_TO_DEBUGGER();
461 return NULL;
462 }
463
464 static const struct dce_hwseq_registers hwseq_reg = {
465 HWSEQ_DCN302_REG_LIST()
466 };
467
468 static const struct dce_hwseq_shift hwseq_shift = {
469 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
470 };
471
472 static const struct dce_hwseq_mask hwseq_mask = {
473 HWSEQ_DCN302_MASK_SH_LIST(_MASK)
474 };
475
dcn302_hwseq_create(struct dc_context * ctx)476 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
477 {
478 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
479
480 if (hws) {
481 hws->ctx = ctx;
482 hws->regs = &hwseq_reg;
483 hws->shifts = &hwseq_shift;
484 hws->masks = &hwseq_mask;
485 }
486 return hws;
487 }
488
489 #define hubp_regs(id)\
490 [id] = { HUBP_REG_LIST_DCN30(id) }
491
492 static const struct dcn_hubp2_registers hubp_regs[] = {
493 hubp_regs(0),
494 hubp_regs(1),
495 hubp_regs(2),
496 hubp_regs(3),
497 hubp_regs(4)
498 };
499
500 static const struct dcn_hubp2_shift hubp_shift = {
501 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
502 };
503
504 static const struct dcn_hubp2_mask hubp_mask = {
505 HUBP_MASK_SH_LIST_DCN30(_MASK)
506 };
507
dcn302_hubp_create(struct dc_context * ctx,uint32_t inst)508 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
509 {
510 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
511
512 if (!hubp2)
513 return NULL;
514
515 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
516 return &hubp2->base;
517
518 BREAK_TO_DEBUGGER();
519 kfree(hubp2);
520 return NULL;
521 }
522
523 #define dpp_regs(id)\
524 [id] = { DPP_REG_LIST_DCN30(id) }
525
526 static const struct dcn3_dpp_registers dpp_regs[] = {
527 dpp_regs(0),
528 dpp_regs(1),
529 dpp_regs(2),
530 dpp_regs(3),
531 dpp_regs(4)
532 };
533
534 static const struct dcn3_dpp_shift tf_shift = {
535 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
536 };
537
538 static const struct dcn3_dpp_mask tf_mask = {
539 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
540 };
541
dcn302_dpp_create(struct dc_context * ctx,uint32_t inst)542 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
543 {
544 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
545
546 if (!dpp)
547 return NULL;
548
549 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
550 return &dpp->base;
551
552 BREAK_TO_DEBUGGER();
553 kfree(dpp);
554 return NULL;
555 }
556
557 #define opp_regs(id)\
558 [id] = { OPP_REG_LIST_DCN30(id) }
559
560 static const struct dcn20_opp_registers opp_regs[] = {
561 opp_regs(0),
562 opp_regs(1),
563 opp_regs(2),
564 opp_regs(3),
565 opp_regs(4)
566 };
567
568 static const struct dcn20_opp_shift opp_shift = {
569 OPP_MASK_SH_LIST_DCN20(__SHIFT)
570 };
571
572 static const struct dcn20_opp_mask opp_mask = {
573 OPP_MASK_SH_LIST_DCN20(_MASK)
574 };
575
dcn302_opp_create(struct dc_context * ctx,uint32_t inst)576 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
577 {
578 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
579
580 if (!opp) {
581 BREAK_TO_DEBUGGER();
582 return NULL;
583 }
584
585 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
586 return &opp->base;
587 }
588
589 #define optc_regs(id)\
590 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
591
592 static const struct dcn_optc_registers optc_regs[] = {
593 optc_regs(0),
594 optc_regs(1),
595 optc_regs(2),
596 optc_regs(3),
597 optc_regs(4)
598 };
599
600 static const struct dcn_optc_shift optc_shift = {
601 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
602 };
603
604 static const struct dcn_optc_mask optc_mask = {
605 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
606 };
607
dcn302_timing_generator_create(struct dc_context * ctx,uint32_t instance)608 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
609 {
610 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
611
612 if (!tgn10)
613 return NULL;
614
615 tgn10->base.inst = instance;
616 tgn10->base.ctx = ctx;
617
618 tgn10->tg_regs = &optc_regs[instance];
619 tgn10->tg_shift = &optc_shift;
620 tgn10->tg_mask = &optc_mask;
621
622 dcn30_timing_generator_init(tgn10);
623
624 return &tgn10->base;
625 }
626
627 static const struct dcn30_mpc_registers mpc_regs = {
628 MPC_REG_LIST_DCN3_0(0),
629 MPC_REG_LIST_DCN3_0(1),
630 MPC_REG_LIST_DCN3_0(2),
631 MPC_REG_LIST_DCN3_0(3),
632 MPC_REG_LIST_DCN3_0(4),
633 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
634 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
635 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
636 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
637 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
638 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
639 MPC_RMU_REG_LIST_DCN3AG(0),
640 MPC_RMU_REG_LIST_DCN3AG(1),
641 MPC_RMU_REG_LIST_DCN3AG(2),
642 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
643 };
644
645 static const struct dcn30_mpc_shift mpc_shift = {
646 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
647 };
648
649 static const struct dcn30_mpc_mask mpc_mask = {
650 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
651 };
652
dcn302_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)653 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
654 {
655 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
656
657 if (!mpc30)
658 return NULL;
659
660 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
661
662 return &mpc30->base;
663 }
664
665 #define dsc_regsDCN20(id)\
666 [id] = { DSC_REG_LIST_DCN20(id) }
667
668 static const struct dcn20_dsc_registers dsc_regs[] = {
669 dsc_regsDCN20(0),
670 dsc_regsDCN20(1),
671 dsc_regsDCN20(2),
672 dsc_regsDCN20(3),
673 dsc_regsDCN20(4)
674 };
675
676 static const struct dcn20_dsc_shift dsc_shift = {
677 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
678 };
679
680 static const struct dcn20_dsc_mask dsc_mask = {
681 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
682 };
683
dcn302_dsc_create(struct dc_context * ctx,uint32_t inst)684 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
685 {
686 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
687
688 if (!dsc) {
689 BREAK_TO_DEBUGGER();
690 return NULL;
691 }
692
693 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
694 return &dsc->base;
695 }
696
697 #define dwbc_regs_dcn3(id)\
698 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
699
700 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
701 dwbc_regs_dcn3(0)
702 };
703
704 static const struct dcn30_dwbc_shift dwbc30_shift = {
705 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
706 };
707
708 static const struct dcn30_dwbc_mask dwbc30_mask = {
709 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
710 };
711
dcn302_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)712 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
713 {
714 int i;
715 uint32_t pipe_count = pool->res_cap->num_dwb;
716
717 for (i = 0; i < pipe_count; i++) {
718 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
719
720 if (!dwbc30) {
721 dm_error("DC: failed to create dwbc30!\n");
722 return false;
723 }
724
725 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
726
727 pool->dwbc[i] = &dwbc30->base;
728 }
729 return true;
730 }
731
732 #define mcif_wb_regs_dcn3(id)\
733 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
734
735 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
736 mcif_wb_regs_dcn3(0)
737 };
738
739 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
740 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
741 };
742
743 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
744 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
745 };
746
dcn302_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)747 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
748 {
749 int i;
750 uint32_t pipe_count = pool->res_cap->num_dwb;
751
752 for (i = 0; i < pipe_count; i++) {
753 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
754
755 if (!mcif_wb30) {
756 dm_error("DC: failed to create mcif_wb30!\n");
757 return false;
758 }
759
760 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
761
762 pool->mcif_wb[i] = &mcif_wb30->base;
763 }
764 return true;
765 }
766
767 #define aux_engine_regs(id)\
768 [id] = {\
769 AUX_COMMON_REG_LIST0(id), \
770 .AUXN_IMPCAL = 0, \
771 .AUXP_IMPCAL = 0, \
772 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
773 }
774
775 static const struct dce110_aux_registers aux_engine_regs[] = {
776 aux_engine_regs(0),
777 aux_engine_regs(1),
778 aux_engine_regs(2),
779 aux_engine_regs(3),
780 aux_engine_regs(4)
781 };
782
783 static const struct dce110_aux_registers_shift aux_shift = {
784 DCN_AUX_MASK_SH_LIST(__SHIFT)
785 };
786
787 static const struct dce110_aux_registers_mask aux_mask = {
788 DCN_AUX_MASK_SH_LIST(_MASK)
789 };
790
dcn302_aux_engine_create(struct dc_context * ctx,uint32_t inst)791 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
792 {
793 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
794
795 if (!aux_engine)
796 return NULL;
797
798 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
799 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
800
801 return &aux_engine->base;
802 }
803
804 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
805
806 static const struct dce_i2c_registers i2c_hw_regs[] = {
807 i2c_inst_regs(1),
808 i2c_inst_regs(2),
809 i2c_inst_regs(3),
810 i2c_inst_regs(4),
811 i2c_inst_regs(5)
812 };
813
814 static const struct dce_i2c_shift i2c_shifts = {
815 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
816 };
817
818 static const struct dce_i2c_mask i2c_masks = {
819 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
820 };
821
dcn302_i2c_hw_create(struct dc_context * ctx,uint32_t inst)822 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
823 {
824 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
825
826 if (!dce_i2c_hw)
827 return NULL;
828
829 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
830
831 return dce_i2c_hw;
832 }
833
834 static const struct encoder_feature_support link_enc_feature = {
835 .max_hdmi_deep_color = COLOR_DEPTH_121212,
836 .max_hdmi_pixel_clock = 600000,
837 .hdmi_ycbcr420_supported = true,
838 .dp_ycbcr420_supported = true,
839 .fec_supported = true,
840 .flags.bits.IS_HBR2_CAPABLE = true,
841 .flags.bits.IS_HBR3_CAPABLE = true,
842 .flags.bits.IS_TPS3_CAPABLE = true,
843 .flags.bits.IS_TPS4_CAPABLE = true
844 };
845
846 #define link_regs(id, phyid)\
847 [id] = {\
848 LE_DCN3_REG_LIST(id), \
849 UNIPHY_DCN2_REG_LIST(phyid), \
850 DPCS_DCN2_REG_LIST(id), \
851 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
852 }
853
854 static const struct dcn10_link_enc_registers link_enc_regs[] = {
855 link_regs(0, A),
856 link_regs(1, B),
857 link_regs(2, C),
858 link_regs(3, D),
859 link_regs(4, E)
860 };
861
862 static const struct dcn10_link_enc_shift le_shift = {
863 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
864 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
865 };
866
867 static const struct dcn10_link_enc_mask le_mask = {
868 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
869 DPCS_DCN2_MASK_SH_LIST(_MASK)
870 };
871
872 #define aux_regs(id)\
873 [id] = { DCN2_AUX_REG_LIST(id) }
874
875 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
876 aux_regs(0),
877 aux_regs(1),
878 aux_regs(2),
879 aux_regs(3),
880 aux_regs(4)
881 };
882
883 #define hpd_regs(id)\
884 [id] = { HPD_REG_LIST(id) }
885
886 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
887 hpd_regs(0),
888 hpd_regs(1),
889 hpd_regs(2),
890 hpd_regs(3),
891 hpd_regs(4)
892 };
893
dcn302_link_encoder_create(const struct encoder_init_data * enc_init_data)894 static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data)
895 {
896 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
897
898 if (!enc20)
899 return NULL;
900
901 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
902 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
903 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
904
905 return &enc20->enc10.base;
906 }
907
908 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
909 { DCN_PANEL_CNTL_REG_LIST() }
910 };
911
912 static const struct dce_panel_cntl_shift panel_cntl_shift = {
913 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
914 };
915
916 static const struct dce_panel_cntl_mask panel_cntl_mask = {
917 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
918 };
919
dcn302_panel_cntl_create(const struct panel_cntl_init_data * init_data)920 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
921 {
922 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
923
924 if (!panel_cntl)
925 return NULL;
926
927 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
928 &panel_cntl_shift, &panel_cntl_mask);
929
930 return &panel_cntl->base;
931 }
932
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)933 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
934 {
935 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
936 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
937 }
938
939 static const struct resource_create_funcs res_create_funcs = {
940 .read_dce_straps = read_dce_straps,
941 .create_audio = dcn302_create_audio,
942 .create_stream_encoder = dcn302_stream_encoder_create,
943 .create_hwseq = dcn302_hwseq_create,
944 };
945
946 static const struct resource_create_funcs res_create_maximus_funcs = {
947 .read_dce_straps = NULL,
948 .create_audio = NULL,
949 .create_stream_encoder = NULL,
950 .create_hwseq = dcn302_hwseq_create,
951 };
952
is_soc_bounding_box_valid(struct dc * dc)953 static bool is_soc_bounding_box_valid(struct dc *dc)
954 {
955 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
956
957 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
958 return true;
959
960 return false;
961 }
962
init_soc_bounding_box(struct dc * dc,struct resource_pool * pool)963 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
964 {
965 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
966 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
967
968 DC_LOGGER_INIT(dc->ctx->logger);
969
970 if (!is_soc_bounding_box_valid(dc)) {
971 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
972 return false;
973 }
974
975 loaded_ip->max_num_otg = pool->pipe_count;
976 loaded_ip->max_num_dpp = pool->pipe_count;
977 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
978 DC_FP_START();
979 dcn20_patch_bounding_box(dc, loaded_bb);
980 DC_FP_END();
981
982 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
983 struct bp_soc_bb_info bb_info = { 0 };
984
985 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
986 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
987
988 DC_FP_START();
989 dcn302_fpu_init_soc_bounding_box(bb_info);
990 DC_FP_END();
991 }
992 }
993
994 return true;
995 }
996
dcn302_resource_destruct(struct resource_pool * pool)997 static void dcn302_resource_destruct(struct resource_pool *pool)
998 {
999 unsigned int i;
1000
1001 for (i = 0; i < pool->stream_enc_count; i++) {
1002 if (pool->stream_enc[i] != NULL) {
1003 if (pool->stream_enc[i]->vpg != NULL) {
1004 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1005 pool->stream_enc[i]->vpg = NULL;
1006 }
1007 if (pool->stream_enc[i]->afmt != NULL) {
1008 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1009 pool->stream_enc[i]->afmt = NULL;
1010 }
1011 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1012 pool->stream_enc[i] = NULL;
1013 }
1014 }
1015
1016 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1017 if (pool->dscs[i] != NULL)
1018 dcn20_dsc_destroy(&pool->dscs[i]);
1019 }
1020
1021 if (pool->mpc != NULL) {
1022 kfree(TO_DCN20_MPC(pool->mpc));
1023 pool->mpc = NULL;
1024 }
1025
1026 if (pool->hubbub != NULL) {
1027 kfree(pool->hubbub);
1028 pool->hubbub = NULL;
1029 }
1030
1031 for (i = 0; i < pool->pipe_count; i++) {
1032 if (pool->dpps[i] != NULL) {
1033 kfree(TO_DCN20_DPP(pool->dpps[i]));
1034 pool->dpps[i] = NULL;
1035 }
1036
1037 if (pool->hubps[i] != NULL) {
1038 kfree(TO_DCN20_HUBP(pool->hubps[i]));
1039 pool->hubps[i] = NULL;
1040 }
1041
1042 if (pool->irqs != NULL)
1043 dal_irq_service_destroy(&pool->irqs);
1044 }
1045
1046 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1047 if (pool->engines[i] != NULL)
1048 dce110_engine_destroy(&pool->engines[i]);
1049 if (pool->hw_i2cs[i] != NULL) {
1050 kfree(pool->hw_i2cs[i]);
1051 pool->hw_i2cs[i] = NULL;
1052 }
1053 if (pool->sw_i2cs[i] != NULL) {
1054 kfree(pool->sw_i2cs[i]);
1055 pool->sw_i2cs[i] = NULL;
1056 }
1057 }
1058
1059 for (i = 0; i < pool->res_cap->num_opp; i++) {
1060 if (pool->opps[i] != NULL)
1061 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1062 }
1063
1064 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1065 if (pool->timing_generators[i] != NULL) {
1066 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1067 pool->timing_generators[i] = NULL;
1068 }
1069 }
1070
1071 for (i = 0; i < pool->res_cap->num_dwb; i++) {
1072 if (pool->dwbc[i] != NULL) {
1073 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1074 pool->dwbc[i] = NULL;
1075 }
1076 if (pool->mcif_wb[i] != NULL) {
1077 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1078 pool->mcif_wb[i] = NULL;
1079 }
1080 }
1081
1082 for (i = 0; i < pool->audio_count; i++) {
1083 if (pool->audios[i])
1084 dce_aud_destroy(&pool->audios[i]);
1085 }
1086
1087 for (i = 0; i < pool->clk_src_count; i++) {
1088 if (pool->clock_sources[i] != NULL)
1089 dcn20_clock_source_destroy(&pool->clock_sources[i]);
1090 }
1091
1092 if (pool->dp_clock_source != NULL)
1093 dcn20_clock_source_destroy(&pool->dp_clock_source);
1094
1095 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1096 if (pool->mpc_lut[i] != NULL) {
1097 dc_3dlut_func_release(pool->mpc_lut[i]);
1098 pool->mpc_lut[i] = NULL;
1099 }
1100 if (pool->mpc_shaper[i] != NULL) {
1101 dc_transfer_func_release(pool->mpc_shaper[i]);
1102 pool->mpc_shaper[i] = NULL;
1103 }
1104 }
1105
1106 for (i = 0; i < pool->pipe_count; i++) {
1107 if (pool->multiple_abms[i] != NULL)
1108 dce_abm_destroy(&pool->multiple_abms[i]);
1109 }
1110
1111 if (pool->psr != NULL)
1112 dmub_psr_destroy(&pool->psr);
1113
1114 if (pool->dccg != NULL)
1115 dcn_dccg_destroy(&pool->dccg);
1116 }
1117
dcn302_destroy_resource_pool(struct resource_pool ** pool)1118 static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1119 {
1120 dcn302_resource_destruct(*pool);
1121 kfree(*pool);
1122 *pool = NULL;
1123 }
1124
dcn302_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1125 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1126 {
1127 DC_FP_START();
1128 dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1129 DC_FP_END();
1130 }
1131
1132 static struct resource_funcs dcn302_res_pool_funcs = {
1133 .destroy = dcn302_destroy_resource_pool,
1134 .link_enc_create = dcn302_link_encoder_create,
1135 .panel_cntl_create = dcn302_panel_cntl_create,
1136 .validate_bandwidth = dcn30_validate_bandwidth,
1137 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1138 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1139 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1140 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1141 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1142 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1143 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1144 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1145 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1146 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1147 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1148 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1149 .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1150 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1151 };
1152
1153 static struct dc_cap_funcs cap_funcs = {
1154 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1155 };
1156
1157 static const struct bios_registers bios_regs = {
1158 NBIO_SR(BIOS_SCRATCH_3),
1159 NBIO_SR(BIOS_SCRATCH_6)
1160 };
1161
1162 static const struct dccg_registers dccg_regs = {
1163 DCCG_REG_LIST_DCN3_02()
1164 };
1165
1166 static const struct dccg_shift dccg_shift = {
1167 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1168 };
1169
1170 static const struct dccg_mask dccg_mask = {
1171 DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1172 };
1173
1174 #define abm_regs(id)\
1175 [id] = { ABM_DCN302_REG_LIST(id) }
1176
1177 static const struct dce_abm_registers abm_regs[] = {
1178 abm_regs(0),
1179 abm_regs(1),
1180 abm_regs(2),
1181 abm_regs(3),
1182 abm_regs(4)
1183 };
1184
1185 static const struct dce_abm_shift abm_shift = {
1186 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1187 };
1188
1189 static const struct dce_abm_mask abm_mask = {
1190 ABM_MASK_SH_LIST_DCN30(_MASK)
1191 };
1192
dcn302_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct resource_pool * pool)1193 static bool dcn302_resource_construct(
1194 uint8_t num_virtual_links,
1195 struct dc *dc,
1196 struct resource_pool *pool)
1197 {
1198 int i;
1199 struct dc_context *ctx = dc->ctx;
1200 struct irq_service_init_data init_data;
1201
1202 ctx->dc_bios->regs = &bios_regs;
1203
1204 pool->res_cap = &res_cap_dcn302;
1205
1206 pool->funcs = &dcn302_res_pool_funcs;
1207
1208 /*************************************************
1209 * Resource + asic cap harcoding *
1210 *************************************************/
1211 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1212 pool->pipe_count = pool->res_cap->num_timing_generator;
1213 pool->mpcc_count = pool->res_cap->num_timing_generator;
1214 dc->caps.max_downscale_ratio = 600;
1215 dc->caps.i2c_speed_in_khz = 100;
1216 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1217 dc->caps.max_cursor_size = 256;
1218 dc->caps.min_horizontal_blanking_period = 80;
1219 dc->caps.dmdata_alloc_size = 2048;
1220 dc->caps.mall_size_per_mem_channel = 4;
1221 /* total size = mall per channel * num channels * 1024 * 1024 */
1222 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1223 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1224 dc->caps.max_slave_planes = 2;
1225 dc->caps.max_slave_yuv_planes = 2;
1226 dc->caps.max_slave_rgb_planes = 2;
1227 dc->caps.post_blend_color_processing = true;
1228 dc->caps.force_dp_tps4_for_cp2520 = true;
1229 dc->caps.extended_aux_timeout_support = true;
1230 dc->caps.dmcub_support = true;
1231
1232 /* Color pipeline capabilities */
1233 dc->caps.color.dpp.dcn_arch = 1;
1234 dc->caps.color.dpp.input_lut_shared = 0;
1235 dc->caps.color.dpp.icsc = 1;
1236 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1237 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1238 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1239 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1240 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1241 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1242 dc->caps.color.dpp.post_csc = 1;
1243 dc->caps.color.dpp.gamma_corr = 1;
1244 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1245
1246 dc->caps.color.dpp.hw_3d_lut = 1;
1247 dc->caps.color.dpp.ogam_ram = 1;
1248 // no OGAM ROM on DCN3
1249 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1250 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1251 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1252 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1253 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1254 dc->caps.color.dpp.ocsc = 0;
1255
1256 dc->caps.color.mpc.gamut_remap = 1;
1257 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1258 dc->caps.color.mpc.ogam_ram = 1;
1259 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1260 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1261 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1262 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1263 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1264 dc->caps.color.mpc.ocsc = 1;
1265
1266 /* read VBIOS LTTPR caps */
1267 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1268 enum bp_result bp_query_result;
1269 uint8_t is_vbios_lttpr_enable = 0;
1270
1271 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1272 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1273 }
1274
1275 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1276 enum bp_result bp_query_result;
1277 uint8_t is_vbios_interop_enabled = 0;
1278
1279 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1280 &is_vbios_interop_enabled);
1281 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1282 }
1283
1284 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1285 dc->debug = debug_defaults_drv;
1286 else
1287 dc->debug = debug_defaults_diags;
1288
1289 // Init the vm_helper
1290 if (dc->vm_helper)
1291 vm_helper_init(dc->vm_helper, 16);
1292
1293 /*************************************************
1294 * Create resources *
1295 *************************************************/
1296
1297 /* Clock Sources for Pixel Clock*/
1298 pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1299 dcn302_clock_source_create(ctx, ctx->dc_bios,
1300 CLOCK_SOURCE_COMBO_PHY_PLL0,
1301 &clk_src_regs[0], false);
1302 pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1303 dcn302_clock_source_create(ctx, ctx->dc_bios,
1304 CLOCK_SOURCE_COMBO_PHY_PLL1,
1305 &clk_src_regs[1], false);
1306 pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1307 dcn302_clock_source_create(ctx, ctx->dc_bios,
1308 CLOCK_SOURCE_COMBO_PHY_PLL2,
1309 &clk_src_regs[2], false);
1310 pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1311 dcn302_clock_source_create(ctx, ctx->dc_bios,
1312 CLOCK_SOURCE_COMBO_PHY_PLL3,
1313 &clk_src_regs[3], false);
1314 pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1315 dcn302_clock_source_create(ctx, ctx->dc_bios,
1316 CLOCK_SOURCE_COMBO_PHY_PLL4,
1317 &clk_src_regs[4], false);
1318
1319 pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1320
1321 /* todo: not reuse phy_pll registers */
1322 pool->dp_clock_source =
1323 dcn302_clock_source_create(ctx, ctx->dc_bios,
1324 CLOCK_SOURCE_ID_DP_DTO,
1325 &clk_src_regs[0], true);
1326
1327 for (i = 0; i < pool->clk_src_count; i++) {
1328 if (pool->clock_sources[i] == NULL) {
1329 dm_error("DC: failed to create clock sources!\n");
1330 BREAK_TO_DEBUGGER();
1331 goto create_fail;
1332 }
1333 }
1334
1335 /* DCCG */
1336 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1337 if (pool->dccg == NULL) {
1338 dm_error("DC: failed to create dccg!\n");
1339 BREAK_TO_DEBUGGER();
1340 goto create_fail;
1341 }
1342
1343 /* PP Lib and SMU interfaces */
1344 init_soc_bounding_box(dc, pool);
1345
1346 /* DML */
1347 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1348
1349 /* IRQ */
1350 init_data.ctx = dc->ctx;
1351 pool->irqs = dal_irq_service_dcn302_create(&init_data);
1352 if (!pool->irqs)
1353 goto create_fail;
1354
1355 /* HUBBUB */
1356 pool->hubbub = dcn302_hubbub_create(ctx);
1357 if (pool->hubbub == NULL) {
1358 BREAK_TO_DEBUGGER();
1359 dm_error("DC: failed to create hubbub!\n");
1360 goto create_fail;
1361 }
1362
1363 /* HUBPs, DPPs, OPPs and TGs */
1364 for (i = 0; i < pool->pipe_count; i++) {
1365 pool->hubps[i] = dcn302_hubp_create(ctx, i);
1366 if (pool->hubps[i] == NULL) {
1367 BREAK_TO_DEBUGGER();
1368 dm_error("DC: failed to create hubps!\n");
1369 goto create_fail;
1370 }
1371
1372 pool->dpps[i] = dcn302_dpp_create(ctx, i);
1373 if (pool->dpps[i] == NULL) {
1374 BREAK_TO_DEBUGGER();
1375 dm_error("DC: failed to create dpps!\n");
1376 goto create_fail;
1377 }
1378 }
1379
1380 for (i = 0; i < pool->res_cap->num_opp; i++) {
1381 pool->opps[i] = dcn302_opp_create(ctx, i);
1382 if (pool->opps[i] == NULL) {
1383 BREAK_TO_DEBUGGER();
1384 dm_error("DC: failed to create output pixel processor!\n");
1385 goto create_fail;
1386 }
1387 }
1388
1389 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1390 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1391 if (pool->timing_generators[i] == NULL) {
1392 BREAK_TO_DEBUGGER();
1393 dm_error("DC: failed to create tg!\n");
1394 goto create_fail;
1395 }
1396 }
1397 pool->timing_generator_count = i;
1398
1399 /* PSR */
1400 pool->psr = dmub_psr_create(ctx);
1401 if (pool->psr == NULL) {
1402 dm_error("DC: failed to create psr!\n");
1403 BREAK_TO_DEBUGGER();
1404 goto create_fail;
1405 }
1406
1407 /* ABMs */
1408 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1409 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1410 if (pool->multiple_abms[i] == NULL) {
1411 dm_error("DC: failed to create abm for pipe %d!\n", i);
1412 BREAK_TO_DEBUGGER();
1413 goto create_fail;
1414 }
1415 }
1416
1417 /* MPC and DSC */
1418 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1419 if (pool->mpc == NULL) {
1420 BREAK_TO_DEBUGGER();
1421 dm_error("DC: failed to create mpc!\n");
1422 goto create_fail;
1423 }
1424
1425 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1426 pool->dscs[i] = dcn302_dsc_create(ctx, i);
1427 if (pool->dscs[i] == NULL) {
1428 BREAK_TO_DEBUGGER();
1429 dm_error("DC: failed to create display stream compressor %d!\n", i);
1430 goto create_fail;
1431 }
1432 }
1433
1434 /* DWB and MMHUBBUB */
1435 if (!dcn302_dwbc_create(ctx, pool)) {
1436 BREAK_TO_DEBUGGER();
1437 dm_error("DC: failed to create dwbc!\n");
1438 goto create_fail;
1439 }
1440
1441 if (!dcn302_mmhubbub_create(ctx, pool)) {
1442 BREAK_TO_DEBUGGER();
1443 dm_error("DC: failed to create mcif_wb!\n");
1444 goto create_fail;
1445 }
1446
1447 /* AUX and I2C */
1448 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1449 pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1450 if (pool->engines[i] == NULL) {
1451 BREAK_TO_DEBUGGER();
1452 dm_error("DC:failed to create aux engine!!\n");
1453 goto create_fail;
1454 }
1455 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1456 if (pool->hw_i2cs[i] == NULL) {
1457 BREAK_TO_DEBUGGER();
1458 dm_error("DC:failed to create hw i2c!!\n");
1459 goto create_fail;
1460 }
1461 pool->sw_i2cs[i] = NULL;
1462 }
1463
1464 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1465 if (!resource_construct(num_virtual_links, dc, pool,
1466 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1467 &res_create_funcs : &res_create_maximus_funcs)))
1468 goto create_fail;
1469
1470 /* HW Sequencer and Plane caps */
1471 dcn302_hw_sequencer_construct(dc);
1472
1473 dc->caps.max_planes = pool->pipe_count;
1474
1475 for (i = 0; i < dc->caps.max_planes; ++i)
1476 dc->caps.planes[i] = plane_cap;
1477
1478 dc->cap_funcs = cap_funcs;
1479
1480 return true;
1481
1482 create_fail:
1483
1484 dcn302_resource_destruct(pool);
1485
1486 return false;
1487 }
1488
dcn302_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)1489 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1490 {
1491 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1492
1493 if (!pool)
1494 return NULL;
1495
1496 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1497 return pool;
1498
1499 BREAK_TO_DEBUGGER();
1500 kfree(pool);
1501 return NULL;
1502 }
1503