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Searched refs:cvmx_write_csr (Results 1 – 25 of 48) sorted by relevance

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/linux-5.19.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-rgmii.c109 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in cvmx_helper_rgmii_internal_loopback()
110 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); in cvmx_helper_rgmii_internal_loopback()
111 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); in cvmx_helper_rgmii_internal_loopback()
112 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback()
114 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
116 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
118 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); in cvmx_helper_rgmii_internal_loopback()
120 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); in cvmx_helper_rgmii_internal_loopback()
138 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); in __cvmx_helper_errata_asx_pass1()
140 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); in __cvmx_helper_errata_asx_pass1()
[all …]
Dcvmx-helper-xaui.c78 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_xaui_probe()
100 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); in __cvmx_helper_xaui_probe()
128 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); in __cvmx_helper_xaui_enable()
136 cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); in __cvmx_helper_xaui_enable()
140 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); in __cvmx_helper_xaui_enable()
142 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_enable()
144 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); in __cvmx_helper_xaui_enable()
153 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); in __cvmx_helper_xaui_enable()
165 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); in __cvmx_helper_xaui_enable()
186 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); in __cvmx_helper_xaui_enable()
[all …]
Dcvmx-spi.c208 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb()
210 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb()
213 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb()
214 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb()
217 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); in cvmx_spi_reset_cb()
238 cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), in cvmx_spi_reset_cb()
243 cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), in cvmx_spi_reset_cb()
248 cvmx_write_csr(CVMX_SPXX_INT_REG(interface), in cvmx_spi_reset_cb()
250 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); in cvmx_spi_reset_cb()
251 cvmx_write_csr(CVMX_STXX_INT_REG(interface), in cvmx_spi_reset_cb()
[all …]
Dcvmx-helper-sgmii.c62 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_one_time()
82 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
103 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
118 cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG in __cvmx_helper_sgmii_hardware_init_one_time()
153 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link()
172 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link()
214 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); in __cvmx_helper_sgmii_hardware_init_link_speed()
257 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
258 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); in __cvmx_helper_sgmii_hardware_init_link_speed()
265 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
[all …]
Dcvmx-pko.c107 cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64); in __cvmx_pko_iport_config()
133 cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko_port_map_o68()
154 cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko_port_map_o68()
198 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); in cvmx_pko_initialize_global()
220 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global()
222 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global()
225 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global()
227 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global()
252 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); in cvmx_pko_enable()
263 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); in cvmx_pko_disable()
[all …]
Dcvmx-boot-vector.c147 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); in cvmx_boot_vector_init()
148 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v); in cvmx_boot_vector_init()
150 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8); in cvmx_boot_vector_init()
151 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem); in cvmx_boot_vector_init()
152 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); in cvmx_boot_vector_init()
Dcvmx-helper-util.c107 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); in cvmx_helper_setup_red_queue()
116 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); in cvmx_helper_setup_red_queue()
147 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), in cvmx_helper_setup_red()
158 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); in cvmx_helper_setup_red()
164 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); in cvmx_helper_setup_red()
191 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); in __cvmx_helper_setup_gmx()
211 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); in __cvmx_helper_setup_gmx()
242 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); in __cvmx_helper_setup_gmx()
273 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), in __cvmx_helper_setup_gmx()
Dcvmx-interrupt-decodes.c56 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), in __cvmx_interrupt_gmxx_rxx_int_en_enable()
229 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); in __cvmx_interrupt_gmxx_rxx_int_en_enable()
239 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), in __cvmx_interrupt_pcsx_intx_en_reg_enable()
272 cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); in __cvmx_interrupt_pcsx_intx_en_reg_enable()
281 cvmx_write_csr(CVMX_PCSXX_INT_REG(index), in __cvmx_interrupt_pcsxx_int_en_reg_enable()
302 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); in __cvmx_interrupt_pcsxx_int_en_reg_enable()
312 cvmx_write_csr(CVMX_SPXX_INT_REG(index), in __cvmx_interrupt_spxx_int_msk_enable()
343 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); in __cvmx_interrupt_spxx_int_msk_enable()
352 cvmx_write_csr(CVMX_STXX_INT_REG(index), in __cvmx_interrupt_stxx_int_msk_enable()
377 cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); in __cvmx_interrupt_stxx_int_msk_enable()
Dcvmx-helper.c659 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); in __cvmx_helper_global_setup_pko()
672 cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64); in __cvmx_helper_global_setup_pko()
822 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); in __cvmx_helper_errata_fix_ipd_ptr_alignment()
844 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment()
902 cvmx_write_csr(CVMX_GMXX_PRTX_CFG in __cvmx_helper_errata_fix_ipd_ptr_alignment()
905 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment()
907 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment()
910 cvmx_write_csr(CVMX_GMXX_RXX_JABBER in __cvmx_helper_errata_fix_ipd_ptr_alignment()
913 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX in __cvmx_helper_errata_fix_ipd_ptr_alignment()
945 cvmx_write_csr(CVMX_GMXX_PRTX_CFG in __cvmx_helper_errata_fix_ipd_ptr_alignment()
[all …]
Dcvmx-l2c.c102 cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask); in cvmx_l2c_set_core_way_partition()
119 cvmx_write_csr(CVMX_L2C_SPAR0, in cvmx_l2c_set_core_way_partition()
124 cvmx_write_csr(CVMX_L2C_SPAR1, in cvmx_l2c_set_core_way_partition()
129 cvmx_write_csr(CVMX_L2C_SPAR2, in cvmx_l2c_set_core_way_partition()
134 cvmx_write_csr(CVMX_L2C_SPAR3, in cvmx_l2c_set_core_way_partition()
154 cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask); in cvmx_l2c_set_hw_way_partition()
156 cvmx_write_csr(CVMX_L2C_SPAR4, in cvmx_l2c_set_hw_way_partition()
201 cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64); in cvmx_l2c_config_perf()
228 cvmx_write_csr(CVMX_L2C_TADX_PRF(tad), in cvmx_l2c_config_perf()
365 cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); in cvmx_l2c_lock_line()
[all …]
Dcvmx-helper-jtag.c69 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_init()
96 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_shift()
140 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_update()
/linux-5.19.10/arch/mips/include/asm/octeon/
Dcvmx-ipd.h95 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); in cvmx_ipd_config()
99 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); in cvmx_ipd_config()
103 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); in cvmx_ipd_config()
107 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); in cvmx_ipd_config()
111 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); in cvmx_ipd_config()
115 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); in cvmx_ipd_config()
120 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); in cvmx_ipd_config()
142 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_enable()
153 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_disable()
204 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
[all …]
Dcvmx-pip.h296 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); in cvmx_pip_config_port()
297 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); in cvmx_pip_config_port()
327 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
343 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); in cvmx_pip_config_vlan_qos()
357 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); in cvmx_pip_config_diffserv_qos()
387 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); in cvmx_pip_get_port_status()
470 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); in cvmx_pip_config_crc()
474 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); in cvmx_pip_config_crc()
493 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_clear()
519 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_set()
/linux-5.19.10/arch/mips/cavium-octeon/
Docteon-irq.c313 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable()
322 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable()
345 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_enable_local()
354 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_enable_local()
377 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); in octeon_irq_ciu_disable_local()
386 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); in octeon_irq_ciu_disable_local()
417 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_disable_all()
419 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_disable_all()
450 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); in octeon_irq_ciu_enable_all()
452 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); in octeon_irq_ciu_enable_all()
[all …]
Docteon-usb.c257 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); in dwc3_octeon_config_power()
262 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); in dwc3_octeon_config_power()
267 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); in dwc3_octeon_config_power()
274 cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); in dwc3_octeon_config_power()
280 cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); in dwc3_octeon_config_power()
363 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
368 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
380 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
390 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
427 cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); in dwc3_octeon_clocks_start()
[all …]
Dsetup.c211 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); in octeon_generic_shutdown()
213 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); in octeon_generic_shutdown()
281 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); in octeon_crash_smp_send_stop()
433 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); in octeon_restart()
435 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); in octeon_restart()
441 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); in octeon_restart()
443 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); in octeon_restart()
460 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); in octeon_kill_core()
477 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); in octeon_halt()
478 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); in octeon_halt()
[all …]
Dsmp.c79 cvmx_write_csr(mbox_clrx, action); in mailbox_interrupt()
106 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); in octeon_send_ipi_single()
261 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); in octeon_prepare_cpus()
338 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); in octeon_cpu_die()
339 cvmx_write_csr(CVMX_CIU_PP_RST, 0); in octeon_cpu_die()
386 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); in octeon_update_boot_vector()
387 cvmx_write_csr(CVMX_CIU_PP_RST, 0); in octeon_update_boot_vector()
396 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); in octeon_update_boot_vector()
Docteon-platform.c107 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); in octeon2_usb_clocks_start()
116 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), in octeon2_usb_clocks_start()
137 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
156 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
188 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
192 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
195 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
205 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
215 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
219 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
[all …]
/linux-5.19.10/arch/mips/pci/
Dpcie-octeon.c178 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); in cvmx_pcie_cfgx_read()
185 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64); in cvmx_pcie_cfgx_read()
207 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); in cvmx_pcie_cfgx_write()
213 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64); in cvmx_pcie_cfgx_write()
446 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); in __cvmx_pcie_rc_initialize_config_space()
461 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64); in __cvmx_pcie_rc_initialize_config_space()
465 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64); in __cvmx_pcie_rc_initialize_config_space()
618 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); in __cvmx_pcie_rc_initialize_link_gen1()
624 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); in __cvmx_pcie_rc_initialize_link_gen1()
645 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); in __cvmx_pcie_rc_initialize_link_gen1()
[all …]
/linux-5.19.10/drivers/net/ethernet/cavium/octeon/
Docteon_mgmt.c165 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); in octeon_mgmt_set_rx_irq()
177 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); in octeon_mgmt_set_tx_irq()
249 cvmx_write_csr(p->mix + MIX_IRING2, 1); in octeon_mgmt_rx_fill_ring()
285 cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); in octeon_mgmt_clean_tx_buffers()
302 cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0); in octeon_mgmt_clean_tx_buffers()
472 cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); in octeon_mgmt_receive_one()
524 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_reset_hw()
529 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_reset_hw()
611 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); in octeon_mgmt_set_rx_filtering()
618 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); in octeon_mgmt_set_rx_filtering()
[all …]
/linux-5.19.10/drivers/staging/octeon/
Dethernet-rx.c203 cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), in cvm_oct_poll()
208 cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), in cvm_oct_poll()
234 cvmx_write_csr(CVMX_SSO_WQ_IQ_DIS, in cvm_oct_poll()
236 cvmx_write_csr(CVMX_SSO_WQ_INT, in cvm_oct_poll()
244 cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64); in cvm_oct_poll()
390 cvmx_write_csr(CVMX_SSO_PPX_GRP_MSK(coreid), old_group_mask); in cvm_oct_poll()
393 cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask); in cvm_oct_poll()
496 cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64); in cvm_oct_rx_initialize()
500 cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64); in cvm_oct_rx_initialize()
508 cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), int_thr.u64); in cvm_oct_rx_initialize()
[all …]
Dethernet.c160 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); in cvm_oct_configure_common_hw()
261 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface), in cvm_oct_common_change_mtu()
273 cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface), in cvm_oct_common_change_mtu()
281 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface), in cvm_oct_common_change_mtu()
326 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), in cvm_oct_common_set_multicast_list()
329 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface), in cvm_oct_common_set_multicast_list()
332 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN in cvm_oct_common_set_multicast_list()
335 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN in cvm_oct_common_set_multicast_list()
338 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), in cvm_oct_common_set_multicast_list()
362 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), in cvm_oct_set_mac_filter()
[all …]
Dethernet-spi.c86 cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64); in cvm_oct_spi_spx_int()
93 cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64); in cvm_oct_spi_spx_int()
99 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), 0); in cvm_oct_spi_spx_int()
100 cvmx_write_csr(CVMX_STXX_INT_MSK(index), 0); in cvm_oct_spi_spx_int()
138 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); in cvm_oct_spi_enable_error_reporting()
149 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); in cvm_oct_spi_enable_error_reporting()
221 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); in cvm_oct_spi_uninit()
222 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); in cvm_oct_spi_uninit()
/linux-5.19.10/drivers/edac/
Docteon_edac-l2c.c41 cvmx_write_csr(CVMX_L2T_ERR, l2t_err_reset.u64); in octeon_l2c_poll_oct1()
56 cvmx_write_csr(CVMX_L2D_ERR, l2d_err_reset.u64); in octeon_l2c_poll_oct1()
100 cvmx_write_csr(CVMX_L2C_ERR_TDTX(tad), err_tdtx_reset.u64); in _octeon_l2c_poll_oct2()
123 cvmx_write_csr(CVMX_L2C_ERR_TTGX(tad), err_ttgx_reset.u64); in _octeon_l2c_poll_oct2()
160 cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); in octeon_l2c_probe()
165 cvmx_write_csr(CVMX_L2T_ERR, l2d_err.u64); in octeon_l2c_probe()
/linux-5.19.10/drivers/ata/
Dpata_octeon_cf.c114 cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); in octeon_cf_set_boot_reg_cfg()
203 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64); in octeon_cf_set_piomode()
206 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1), in octeon_cf_set_piomode()
278 cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); in octeon_cf_set_dmamode()
549 cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64); in octeon_cf_dma_start()
552 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64); in octeon_cf_dma_start()
580 cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); in octeon_cf_dma_start()
613 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); in octeon_cf_dma_finished()
617 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); in octeon_cf_dma_finished()
621 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); in octeon_cf_dma_finished()
[all …]

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