| /linux-5.19.10/drivers/cpufreq/ |
| D | tegra124-cpufreq.c | 21 struct clk *cpu_clk; member
33 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk)); in tegra124_cpu_switch_to_dfll()
37 orig_parent = clk_get_parent(priv->cpu_clk); in tegra124_cpu_switch_to_dfll()
38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
44 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
49 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
74 priv->cpu_clk = of_clk_get_by_name(np, "cpu_g"); in tegra124_cpufreq_probe()
75 if (IS_ERR(priv->cpu_clk)) { in tegra124_cpufreq_probe()
76 ret = PTR_ERR(priv->cpu_clk); in tegra124_cpufreq_probe()
125 clk_put(priv->cpu_clk); in tegra124_cpufreq_probe()
[all …]
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| D | kirkwood-cpufreq.c | 21 struct clk *cpu_clk; member
65 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target()
119 priv.cpu_clk = of_clk_get_by_name(np, "cpu_clk"); in kirkwood_cpufreq_probe()
120 if (IS_ERR(priv.cpu_clk)) { in kirkwood_cpufreq_probe()
122 err = PTR_ERR(priv.cpu_clk); in kirkwood_cpufreq_probe()
126 err = clk_prepare_enable(priv.cpu_clk); in kirkwood_cpufreq_probe()
132 kirkwood_freq_table[0].frequency = clk_get_rate(priv.cpu_clk) / 1000; in kirkwood_cpufreq_probe()
174 clk_disable_unprepare(priv.cpu_clk); in kirkwood_cpufreq_probe()
187 clk_disable_unprepare(priv.cpu_clk); in kirkwood_cpufreq_remove()
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| D | mediatek-cpufreq.c | 45 struct clk *cpu_clk; member
204 struct clk *cpu_clk = policy->clk; in mtk_cpufreq_set_target() local
205 struct clk *armpll = clk_get_parent(cpu_clk); in mtk_cpufreq_set_target()
214 pre_freq_hz = clk_get_rate(cpu_clk); in mtk_cpufreq_set_target()
265 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
278 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
284 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
301 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
303 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
411 info->cpu_clk = clk_get(cpu_dev, "cpu"); in mtk_cpu_dvfs_info_init()
[all …]
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| D | highbank-cpufreq.c | 62 struct clk *cpu_clk; in hb_cpufreq_driver_init() local
82 cpu_clk = clk_get(cpu_dev, NULL); in hb_cpufreq_driver_init()
83 if (IS_ERR(cpu_clk)) { in hb_cpufreq_driver_init()
84 ret = PTR_ERR(cpu_clk); in hb_cpufreq_driver_init()
89 ret = clk_notifier_register(cpu_clk, &hb_cpufreq_clk_nb); in hb_cpufreq_driver_init()
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| D | cpufreq-dt.c | 107 struct clk *cpu_clk; in cpufreq_init() local
118 cpu_clk = clk_get(cpu_dev, NULL); in cpufreq_init()
119 if (IS_ERR(cpu_clk)) { in cpufreq_init()
120 ret = PTR_ERR(cpu_clk); in cpufreq_init()
131 policy->clk = cpu_clk; in cpufreq_init()
149 clk_put(cpu_clk); in cpufreq_init()
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| /linux-5.19.10/arch/arm/mach-mvebu/ |
| D | platsmp.c | 42 struct clk *cpu_clk; in get_cpu_clk() local
47 cpu_clk = of_clk_get(np, 0); in get_cpu_clk()
48 if (WARN_ON(IS_ERR(cpu_clk))) in get_cpu_clk()
50 return cpu_clk; in get_cpu_clk()
104 struct clk *cpu_clk = get_cpu_clk(cpu); in armada_xp_sync_secondary_clk() local
106 if (!cpu_clk || !boot_cpu_clk) in armada_xp_sync_secondary_clk()
109 clk_prepare_enable(cpu_clk); in armada_xp_sync_secondary_clk()
110 clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk)); in armada_xp_sync_secondary_clk()
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| /linux-5.19.10/arch/mips/ar7/ |
| D | time.c | 19 struct clk *cpu_clk; in plat_time_init() local
24 cpu_clk = clk_get(NULL, "cpu"); in plat_time_init()
25 if (IS_ERR(cpu_clk)) { in plat_time_init()
30 mips_hpt_frequency = clk_get_rate(cpu_clk) / 2; in plat_time_init()
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| D | clock.c | 96 static struct clk_rate cpu_clk = { variable
184 base_clock = cpu_clk.rate; in tnetd7300_get_clock()
224 base_clock = cpu_clk.rate; in tnetd7300_set_clock()
252 cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
255 cpu_clk.rate = bus_clk.rate; in tnetd7300_init_clocks()
265 clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate); in tnetd7300_init_clocks()
360 cpu_clk.rate = in tnetd7200_init_clocks()
364 cpu_clk.rate); in tnetd7200_init_clocks()
373 cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul) in tnetd7200_init_clocks()
377 cpu_clk.rate); in tnetd7200_init_clocks()
[all …]
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| /linux-5.19.10/arch/mips/lantiq/xway/ |
| D | clk.c | 144 unsigned int ocp_sel, cpu_clk; in ltq_vr9_fpi_hz() local
147 cpu_clk = ltq_vr9_cpu_hz(); in ltq_vr9_fpi_hz()
153 clk = cpu_clk; in ltq_vr9_fpi_hz()
157 clk = cpu_clk / 2; in ltq_vr9_fpi_hz()
161 clk = (cpu_clk * 2) / 5; in ltq_vr9_fpi_hz()
165 clk = cpu_clk / 3; in ltq_vr9_fpi_hz()
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| /linux-5.19.10/drivers/clk/mvebu/ |
| D | clk-cpu.c | 33 struct cpu_clk { struct
46 #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw) argument
51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_recalc_rate()
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_off_set_rate()
113 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_on_set_rate()
168 struct cpu_clk *cpuclk; in of_cpu_clk_setup()
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| /linux-5.19.10/arch/sh/kernel/cpu/ |
| D | clock-cpg.c | 24 static struct clk cpu_clk = { variable
36 &cpu_clk,
44 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
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| /linux-5.19.10/Documentation/devicetree/bindings/arm/marvell/ |
| D | kirkwood.txt | 12 cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
14 between the "cpu_clk" and the "ddrclk".
26 clock-names = "cpu_clk", "ddrclk", "powersave";
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| /linux-5.19.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap806-quad.dtsi | 24 clocks = <&cpu_clk 0>;
39 clocks = <&cpu_clk 0>;
54 clocks = <&cpu_clk 1>;
69 clocks = <&cpu_clk 1>;
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| D | armada-ap807-quad.dtsi | 24 clocks = <&cpu_clk 0>;
39 clocks = <&cpu_clk 0>;
54 clocks = <&cpu_clk 1>;
69 clocks = <&cpu_clk 1>;
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| D | armada-ap806-dual.dtsi | 24 clocks = <&cpu_clk 0>;
39 clocks = <&cpu_clk 0>;
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| /linux-5.19.10/arch/mips/boot/dts/mscc/ |
| D | luton.dtsi | 16 clocks = <&cpu_clk>;
32 cpu_clk: cpu-clock { label
41 clocks = <&cpu_clk>;
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| D | serval.dtsi | 18 clocks = <&cpu_clk>;
35 cpu_clk: cpu-clock { label
44 clocks = <&cpu_clk>;
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| D | jaguar2.dtsi | 24 clocks = <&cpu_clk>;
36 cpu_clk: cpu-clock { label
45 clocks = <&cpu_clk>;
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| D | ocelot.dtsi | 16 clocks = <&cpu_clk>;
32 cpu_clk: cpu-clock { label
41 clocks = <&cpu_clk>;
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| /linux-5.19.10/Documentation/devicetree/bindings/clock/ |
| D | microchip,lan966x-gck.yaml | 13 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
56 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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| /linux-5.19.10/arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 31 clocks = <&cpu_clk>;
37 clocks = <&cpu_clk>;
53 cpu_clk: clkdiv_cpu { label
57 clock-output-names = "cpu_clk";
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| /linux-5.19.10/drivers/base/ |
| D | arch_topology.c | 298 struct clk *cpu_clk; in topology_parse_cpu_capacity() local
328 cpu_clk = of_clk_get(cpu_node, 0); in topology_parse_cpu_capacity()
329 if (!PTR_ERR_OR_ZERO(cpu_clk)) { in topology_parse_cpu_capacity()
331 clk_get_rate(cpu_clk) / 1000; in topology_parse_cpu_capacity()
332 clk_put(cpu_clk); in topology_parse_cpu_capacity()
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| /linux-5.19.10/drivers/clk/sunxi-ng/ |
| D | ccu-suniv-f1c100s.c | 110 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
320 &cpu_clk.common,
411 [CLK_CPU] = &cpu_clk.common.hw,
520 .common = &cpu_clk.common,
521 .cm = &cpu_clk.mux,
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| /linux-5.19.10/drivers/clk/ralink/ |
| D | clk-mt7621.c | 257 unsigned long cpu_clk; in mt7621_cpu_recalc_rate() local
268 cpu_clk = 500000000; in mt7621_cpu_recalc_rate()
274 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
277 cpu_clk = xtal_clk; in mt7621_cpu_recalc_rate()
280 return cpu_clk / ffiv * ffrac; in mt7621_cpu_recalc_rate()
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| /linux-5.19.10/arch/mips/boot/dts/loongson/ |
| D | loongson64-2k1000.dtsi | 22 clocks = <&cpu_clk>;
34 cpu_clk: cpu_clk { label
|