| /linux-5.19.10/drivers/clk/pxa/ |
| D | clk-pxa.c | 218 rate = freqs[i].cpll; in pxa2xx_determine_rate()
236 rate = freqs[closest_below].cpll; in pxa2xx_determine_rate()
238 rate = freqs[closest_above].cpll; in pxa2xx_determine_rate()
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| D | clk-pxa.h | 137 unsigned long cpll; member
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| D | clk-pxa25x.c | 242 if (pxa25x_freqs[i].cpll == rate) in clk_pxa25x_cpll_set_rate()
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| D | clk-pxa27x.c | 234 if (pxa27x_freqs[i].cpll == rate) in clk_pxa27x_cpll_set_rate()
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| /linux-5.19.10/drivers/clk/samsung/ |
| D | clk-exynos5410.c | 61 apll, cpll, epll, mpll, enumerator
242 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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| D | clk-exynos5250.c | 105 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
741 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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| D | clk-exynos5420.c | 150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1464 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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| /linux-5.19.10/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 19 apll, cpll, dpll, gpll, enumerator
220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
231 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3128.c | 18 apll, dpll, cpll, gpll, enumerator
163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3228.c | 19 apll, dpll, cpll, gpll, enumerator
173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
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| D | clk-rk3328.c | 21 apll, dpll, cpll, gpll, npll, enumerator
221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3368.c | 17 apllb, aplll, dpll, cpll, gpll, npll, enumerator
136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
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| D | clk-rk3288.c | 24 apll, dpll, cpll, gpll, npll, enumerator
230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
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| D | clk-px30.c | 18 apll, dpll, cpll, npll, apll_b_h, apll_b_l, enumerator
191 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3399.c | 19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
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| D | clk-rk3568.c | 23 apll, dpll, gpll, cpll, npll, vpll, enumerator
327 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| /linux-5.19.10/arch/arm64/boot/dts/rockchip/ |
| D | rk3328.dtsi | 786 * We need set cpll child clk div first,
787 * and then set the cpll frequency.
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