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Searched refs:clr_ofs (Results 1 – 25 of 114) sorted by relevance

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/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt8183-ipu_conn.c16 .clr_ofs = 0x8,
22 .clr_ofs = 0x10,
28 .clr_ofs = 0x18,
34 .clr_ofs = 0x1c,
40 .clr_ofs = 0x20,
Dclk-mt8186-vdec.c17 .clr_ofs = 0x4,
23 .clr_ofs = 0x190,
29 .clr_ofs = 0x204,
35 .clr_ofs = 0xc,
Dclk-gate.c21 int clr_ofs; member
62 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); in mtk_cg_clr_bit()
158 int clr_ofs, int sta_ofs, u8 bit, in mtk_clk_register_gate() argument
178 cg->clr_ofs = clr_ofs; in mtk_clk_register_gate()
235 gate->regs->clr_ofs, in mtk_clk_register_gates_with_dev()
Dclk-mt8192-vdec.c17 .clr_ofs = 0x4,
23 .clr_ofs = 0x204,
29 .clr_ofs = 0xc,
Dclk-mt8195-vdec.c15 .clr_ofs = 0x4,
21 .clr_ofs = 0x204,
27 .clr_ofs = 0xc,
Dclk-mt8195-infra_ao.c15 .clr_ofs = 0x84,
21 .clr_ofs = 0x8c,
27 .clr_ofs = 0xa8,
33 .clr_ofs = 0xc4,
39 .clr_ofs = 0xe4,
Dclk-mt2701-aud.c56 .clr_ofs = 0x0,
62 .clr_ofs = 0x10,
68 .clr_ofs = 0x14,
74 .clr_ofs = 0x634,
Dclk-mt8195-vdo1.c15 .clr_ofs = 0x108,
21 .clr_ofs = 0x128,
27 .clr_ofs = 0x138,
33 .clr_ofs = 0x148,
Dclk-mt7622-aud.c57 .clr_ofs = 0x0,
63 .clr_ofs = 0x10,
69 .clr_ofs = 0x14,
75 .clr_ofs = 0x634,
Dclk-mt8195-vpp0.c15 .clr_ofs = 0x28,
21 .clr_ofs = 0x34,
27 .clr_ofs = 0x40,
Dclk-mt8192-mm.c16 .clr_ofs = 0x108,
22 .clr_ofs = 0x118,
28 .clr_ofs = 0x1a8,
Dclk-mt8192-aud.c17 .clr_ofs = 0x0,
23 .clr_ofs = 0x4,
29 .clr_ofs = 0x8,
Dclk-mt7986-eth.c21 .clr_ofs = 0xe4,
41 .clr_ofs = 0xe4,
61 .clr_ofs = 0x30,
Dclk-mt8195-wpe.c15 .clr_ofs = 0x0,
21 .clr_ofs = 0x58,
27 .clr_ofs = 0x5c,
Dclk-mt8186-infra_ao.c15 .clr_ofs = 0x84,
21 .clr_ofs = 0x8c,
27 .clr_ofs = 0xa8,
33 .clr_ofs = 0xc4,
Dclk-mt8195-vdo0.c15 .clr_ofs = 0x108,
21 .clr_ofs = 0x118,
27 .clr_ofs = 0x128,
Dclk-mt8167-vdec.c22 .clr_ofs = 0x4,
28 .clr_ofs = 0xc,
Dclk-mt6779-vdec.c18 .clr_ofs = 0x0004,
24 .clr_ofs = 0x000c,
Dclk-mt8183-vdec.c16 .clr_ofs = 0x4,
22 .clr_ofs = 0xc,
Dclk-mt2712-mm.c17 .clr_ofs = 0x108,
23 .clr_ofs = 0x118,
29 .clr_ofs = 0x228,
Dclk-mt2712-vdec.c17 .clr_ofs = 0x4,
23 .clr_ofs = 0xc,
Dclk-mt6797-vdec.c17 .clr_ofs = 0x0004,
23 .clr_ofs = 0x000c,
Dclk-mt8192-msdc.c17 .clr_ofs = 0xb4,
23 .clr_ofs = 0x0,
Dclk-mt2701-vdec.c17 .clr_ofs = 0x0004,
23 .clr_ofs = 0x000c,
Dclk-mt8192-mdp.c17 .clr_ofs = 0x108,
23 .clr_ofs = 0x128,

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