1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Marvell PXA27x family clocks
4 *
5 * Copyright (C) 2014 Robert Jarzmik
6 *
7 * Heavily inspired from former arch/arm/mach-pxa/clock.c.
8 */
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/of.h>
14 #include <linux/soc/pxa/smemc.h>
15
16 #include <dt-bindings/clock/pxa-clock.h>
17 #include "clk-pxa.h"
18 #include "clk-pxa2xx.h"
19
20 #define KHz 1000
21 #define MHz (1000 * 1000)
22
23 enum {
24 PXA_CORE_13Mhz = 0,
25 PXA_CORE_RUN,
26 PXA_CORE_TURBO,
27 };
28
29 enum {
30 PXA_BUS_13Mhz = 0,
31 PXA_BUS_RUN,
32 };
33
34 enum {
35 PXA_LCD_13Mhz = 0,
36 PXA_LCD_RUN,
37 };
38
39 enum {
40 PXA_MEM_13Mhz = 0,
41 PXA_MEM_SYSTEM_BUS,
42 PXA_MEM_RUN,
43 };
44
45 #define PXA27x_CLKCFG(B, HT, T) \
46 (CLKCFG_FCS | \
47 ((B) ? CLKCFG_FASTBUS : 0) | \
48 ((HT) ? CLKCFG_HALFTURBO : 0) | \
49 ((T) ? CLKCFG_TURBO : 0))
50 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
51
52 /* Define the refresh period in mSec for the SDRAM and the number of rows */
53 #define SDRAM_TREF 64 /* standard 64ms SDRAM */
54
55 static void __iomem *clk_regs;
56
57 static const char * const get_freq_khz[] = {
58 "core", "run", "cpll", "memory",
59 "system_bus"
60 };
61
mdrefr_dri(unsigned int freq_khz)62 static u32 mdrefr_dri(unsigned int freq_khz)
63 {
64 u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
65
66 return (interval - 31) / 32;
67 }
68
69 /*
70 * Get the clock frequency as reflected by CCSR and the turbo flag.
71 * We assume these values have been applied via a fcs.
72 * If info is not 0 we also display the current settings.
73 */
pxa27x_get_clk_frequency_khz(int info)74 unsigned int pxa27x_get_clk_frequency_khz(int info)
75 {
76 struct clk *clk;
77 unsigned long clks[5];
78 int i;
79
80 for (i = 0; i < 5; i++) {
81 clk = clk_get(NULL, get_freq_khz[i]);
82 if (IS_ERR(clk)) {
83 clks[i] = 0;
84 } else {
85 clks[i] = clk_get_rate(clk);
86 clk_put(clk);
87 }
88 }
89 if (info) {
90 pr_info("Run Mode clock: %ld.%02ldMHz\n",
91 clks[1] / 1000000, (clks[1] % 1000000) / 10000);
92 pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
93 clks[2] / 1000000, (clks[2] % 1000000) / 10000);
94 pr_info("Memory clock: %ld.%02ldMHz\n",
95 clks[3] / 1000000, (clks[3] % 1000000) / 10000);
96 pr_info("System bus clock: %ld.%02ldMHz\n",
97 clks[4] / 1000000, (clks[4] % 1000000) / 10000);
98 }
99 return (unsigned int)clks[0] / KHz;
100 }
101
pxa27x_is_ppll_disabled(void)102 bool pxa27x_is_ppll_disabled(void)
103 {
104 unsigned long ccsr = readl(clk_regs + CCSR);
105
106 return ccsr & (1 << CCCR_PPDIS_BIT);
107 }
108
109 #define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
110 bit, is_lp, flags) \
111 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
112 is_lp, CKEN, CKEN_ ## bit, flags)
113 #define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
114 PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
115 div_hp, bit, pxa27x_is_ppll_disabled, 0)
116
117 PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
118 PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
119 PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
120 PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
121 PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
122
123 #define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
124 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
125 CKEN, CKEN_ ## bit, 0)
126 #define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
127 PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
128 CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
129
130 static struct desc_clk_cken pxa27x_clocks[] __initdata = {
131 PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
132 PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
133 PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
134 PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
135 PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
136 PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
137 PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
138 PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
139 PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
140 PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
141 PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
142 PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
143 PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
144 PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
145 PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
146 PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
147 PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
148 PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
149 PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
150 PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
151 PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
152
153 PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
154 pxa27x_32Mhz_bus_parents, 0),
155 PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
156 PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
157 PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
158 pxa27x_lcd_bus_parents, 0),
159 PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
160 pxa27x_membus_parents, 0),
161
162 };
163
164 /*
165 * PXA270 definitions
166 *
167 * For the PXA27x:
168 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
169 *
170 * A = 0 => memory controller clock from table 3-7,
171 * A = 1 => memory controller clock = system bus clock
172 * Run mode frequency = 13 MHz * L
173 * Turbo mode frequency = 13 MHz * L * N
174 * System bus frequency = 13 MHz * L / (B + 1)
175 *
176 * In CCCR:
177 * A = 1
178 * L = 16 oscillator to run mode ratio
179 * 2N = 6 2 * (turbo mode to run mode ratio)
180 *
181 * In CCLKCFG:
182 * B = 1 Fast bus mode
183 * HT = 0 Half-Turbo mode
184 * T = 1 Turbo mode
185 *
186 * For now, just support some of the combinations in table 3-7 of
187 * PXA27x Processor Family Developer's Manual to simplify frequency
188 * change sequences.
189 */
190 static struct pxa2xx_freq pxa27x_freqs[] = {
191 {104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
192 {156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
193 {208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
194 {312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
195 {416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
196 {520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
197 {624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
198 };
199
clk_pxa27x_cpll_get_rate(struct clk_hw * hw,unsigned long parent_rate)200 static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
201 unsigned long parent_rate)
202 {
203 unsigned long clkcfg;
204 unsigned int t, ht;
205 unsigned int l, L, n2, N;
206 unsigned long ccsr = readl(clk_regs + CCSR);
207
208 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
209 t = clkcfg & (1 << 0);
210 ht = clkcfg & (1 << 2);
211
212 l = ccsr & CCSR_L_MASK;
213 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
214 L = l * parent_rate;
215 N = (L * n2) / 2;
216
217 return N;
218 }
219
clk_pxa27x_cpll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)220 static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
221 struct clk_rate_request *req)
222 {
223 return pxa2xx_determine_rate(req, pxa27x_freqs,
224 ARRAY_SIZE(pxa27x_freqs));
225 }
226
clk_pxa27x_cpll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)227 static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
228 unsigned long parent_rate)
229 {
230 int i;
231
232 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
233 for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
234 if (pxa27x_freqs[i].cpll == rate)
235 break;
236
237 if (i >= ARRAY_SIZE(pxa27x_freqs))
238 return -EINVAL;
239
240 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR);
241 return 0;
242 }
243
244 PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
245 RATE_OPS(clk_pxa27x_cpll, "cpll");
246
clk_pxa27x_lcd_base_get_rate(struct clk_hw * hw,unsigned long parent_rate)247 static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
248 unsigned long parent_rate)
249 {
250 unsigned int l, osc_forced;
251 unsigned long ccsr = readl(clk_regs + CCSR);
252 unsigned long cccr = readl(clk_regs + CCCR);
253
254 l = ccsr & CCSR_L_MASK;
255 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
256 if (osc_forced) {
257 if (cccr & (1 << CCCR_LCD_26_BIT))
258 return parent_rate * 2;
259 else
260 return parent_rate;
261 }
262
263 if (l <= 7)
264 return parent_rate;
265 if (l <= 16)
266 return parent_rate / 2;
267 return parent_rate / 4;
268 }
269
clk_pxa27x_lcd_base_get_parent(struct clk_hw * hw)270 static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
271 {
272 unsigned int osc_forced;
273 unsigned long ccsr = readl(clk_regs + CCSR);
274
275 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
276 if (osc_forced)
277 return PXA_LCD_13Mhz;
278 else
279 return PXA_LCD_RUN;
280 }
281
282 PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
283 MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
284
pxa27x_register_plls(void)285 static void __init pxa27x_register_plls(void)
286 {
287 clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
288 CLK_GET_RATE_NOCACHE,
289 13 * MHz);
290 clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
291 clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
292 CLK_GET_RATE_NOCACHE,
293 32768 * KHz));
294 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
295 clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
296 }
297
clk_pxa27x_core_get_parent(struct clk_hw * hw)298 static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
299 {
300 unsigned long clkcfg;
301 unsigned int t, ht, osc_forced;
302 unsigned long ccsr = readl(clk_regs + CCSR);
303
304 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
305 if (osc_forced)
306 return PXA_CORE_13Mhz;
307
308 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
309 t = clkcfg & (1 << 0);
310 ht = clkcfg & (1 << 2);
311
312 if (ht || t)
313 return PXA_CORE_TURBO;
314 return PXA_CORE_RUN;
315 }
316
clk_pxa27x_core_set_parent(struct clk_hw * hw,u8 index)317 static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
318 {
319 if (index > PXA_CORE_TURBO)
320 return -EINVAL;
321
322 pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
323
324 return 0;
325 }
326
clk_pxa27x_core_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)327 static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
328 struct clk_rate_request *req)
329 {
330 return __clk_mux_determine_rate(hw, req);
331 }
332
333 PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
334 MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
335
clk_pxa27x_run_get_rate(struct clk_hw * hw,unsigned long parent_rate)336 static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
337 unsigned long parent_rate)
338 {
339 unsigned long ccsr = readl(clk_regs + CCSR);
340 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
341
342 return (parent_rate / n2) * 2;
343 }
344 PARENTS(clk_pxa27x_run) = { "cpll" };
345 RATE_RO_OPS(clk_pxa27x_run, "run");
346
pxa27x_register_core(void)347 static void __init pxa27x_register_core(void)
348 {
349 clkdev_pxa_register(CLK_NONE, "cpll", NULL,
350 clk_register_clk_pxa27x_cpll());
351 clkdev_pxa_register(CLK_NONE, "run", NULL,
352 clk_register_clk_pxa27x_run());
353 clkdev_pxa_register(CLK_CORE, "core", NULL,
354 clk_register_clk_pxa27x_core());
355 }
356
clk_pxa27x_system_bus_get_rate(struct clk_hw * hw,unsigned long parent_rate)357 static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
358 unsigned long parent_rate)
359 {
360 unsigned long clkcfg;
361 unsigned int b, osc_forced;
362 unsigned long ccsr = readl(clk_regs + CCSR);
363
364 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
365 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
366 b = clkcfg & (1 << 3);
367
368 if (osc_forced)
369 return parent_rate;
370 if (b)
371 return parent_rate;
372 else
373 return parent_rate / 2;
374 }
375
clk_pxa27x_system_bus_get_parent(struct clk_hw * hw)376 static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
377 {
378 unsigned int osc_forced;
379 unsigned long ccsr = readl(clk_regs + CCSR);
380
381 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
382 if (osc_forced)
383 return PXA_BUS_13Mhz;
384 else
385 return PXA_BUS_RUN;
386 }
387
388 PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
389 MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
390
clk_pxa27x_memory_get_rate(struct clk_hw * hw,unsigned long parent_rate)391 static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
392 unsigned long parent_rate)
393 {
394 unsigned int a, l, osc_forced;
395 unsigned long cccr = readl(clk_regs + CCCR);
396 unsigned long ccsr = readl(clk_regs + CCSR);
397
398 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
399 a = cccr & (1 << CCCR_A_BIT);
400 l = ccsr & CCSR_L_MASK;
401
402 if (osc_forced || a)
403 return parent_rate;
404 if (l <= 10)
405 return parent_rate;
406 if (l <= 20)
407 return parent_rate / 2;
408 return parent_rate / 4;
409 }
410
clk_pxa27x_memory_get_parent(struct clk_hw * hw)411 static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
412 {
413 unsigned int osc_forced, a;
414 unsigned long cccr = readl(clk_regs + CCCR);
415 unsigned long ccsr = readl(clk_regs + CCSR);
416
417 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
418 a = cccr & (1 << CCCR_A_BIT);
419 if (osc_forced)
420 return PXA_MEM_13Mhz;
421 if (a)
422 return PXA_MEM_SYSTEM_BUS;
423 else
424 return PXA_MEM_RUN;
425 }
426
427 PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
428 MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
429
430 #define DUMMY_CLK(_con_id, _dev_id, _parent) \
431 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
432 struct dummy_clk {
433 const char *con_id;
434 const char *dev_id;
435 const char *parent;
436 };
437 static struct dummy_clk dummy_clks[] __initdata = {
438 DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
439 DUMMY_CLK(NULL, "pxa-rtc", "osc_32_768khz"),
440 DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
441 DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
442 };
443
pxa27x_dummy_clocks_init(void)444 static void __init pxa27x_dummy_clocks_init(void)
445 {
446 struct clk *clk;
447 struct dummy_clk *d;
448 const char *name;
449 int i;
450
451 for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
452 d = &dummy_clks[i];
453 name = d->dev_id ? d->dev_id : d->con_id;
454 clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
455 clk_register_clkdev(clk, d->con_id, d->dev_id);
456 }
457 }
458
pxa27x_base_clocks_init(void)459 static void __init pxa27x_base_clocks_init(void)
460 {
461 pxa27x_register_plls();
462 pxa27x_register_core();
463 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
464 clk_register_clk_pxa27x_system_bus());
465 clkdev_pxa_register(CLK_NONE, "memory", NULL,
466 clk_register_clk_pxa27x_memory());
467 clk_register_clk_pxa27x_lcd_base();
468 }
469
pxa27x_clocks_init(void __iomem * regs)470 int __init pxa27x_clocks_init(void __iomem *regs)
471 {
472 clk_regs = regs;
473 pxa27x_base_clocks_init();
474 pxa27x_dummy_clocks_init();
475 return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), regs);
476 }
477
pxa27x_dt_clocks_init(struct device_node * np)478 static void __init pxa27x_dt_clocks_init(struct device_node *np)
479 {
480 pxa27x_clocks_init(ioremap(0x41300000ul, 0x10));
481 clk_pxa_dt_common_init(np);
482 }
483 CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
484