Searched refs:clk_period_ps (Results 1 – 4 of 4) sorted by relevance
1038 u32 clk_period_ps) in create_timings_aligned() argument1043 if (clk_period_ps == 0) in create_timings_aligned()1050 val = dmc->timings->tRFC / clk_period_ps; in create_timings_aligned()1051 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; in create_timings_aligned()1056 val = dmc->timings->tRRD / clk_period_ps; in create_timings_aligned()1057 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; in create_timings_aligned()1062 val = dmc->timings->tRPab / clk_period_ps; in create_timings_aligned()1063 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; in create_timings_aligned()1068 val = dmc->timings->tRCD / clk_period_ps; in create_timings_aligned()1069 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; in create_timings_aligned()[all …]
287 u32 taxi_bw, clk_period_ps; in sparx5_dsm_calendar_calc() local289 clk_period_ps = sparx5_clk_period(sparx5->coreclock); in sparx5_dsm_calendar_calc()290 taxi_bw = 128 * 1000000 / clk_period_ps; in sparx5_dsm_calendar_calc()291 slow_mode = !!(clk_period_ps > 2000); in sparx5_dsm_calendar_calc()365 (adjusted_speed * clk_period_ps); in sparx5_dsm_calendar_calc()
601 u32 clk_period_ps = 1600; /* 625Mhz for now */ in sparx5_port_fwd_urg() local623 return urg / clk_period_ps - 1; in sparx5_port_fwd_urg()
167 u64 clk_period_ps; in aspeed_sdhci_phase_to_tap() local184 clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); in aspeed_sdhci_phase_to_tap()185 phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL); in aspeed_sdhci_phase_to_tap()