Searched refs:bcpu (Results 1 – 4 of 4) sorted by relevance
146 int bcpu = uv_cpu_blade_processor_id(cpu); in uv_rtc_allocate_timers() local163 head->cpu[bcpu].lcpu = cpu; in uv_rtc_allocate_timers()164 head->cpu[bcpu].expires = ULLONG_MAX; in uv_rtc_allocate_timers()174 int c, bcpu = -1; in uv_rtc_find_next_timer() local180 bcpu = c; in uv_rtc_find_next_timer()184 if (bcpu >= 0) { in uv_rtc_find_next_timer()185 head->next_cpu = bcpu; in uv_rtc_find_next_timer()186 c = head->cpu[bcpu].lcpu; in uv_rtc_find_next_timer()206 int bcpu = uv_cpu_blade_processor_id(cpu); in uv_rtc_set_timer() local207 u64 *t = &head->cpu[bcpu].expires; in uv_rtc_set_timer()[all …]
133 struct gnet_stats_basic_sync *bcpu = per_cpu_ptr(cpu, i); in gnet_stats_add_basic_cpu() local138 start = u64_stats_fetch_begin_irq(&bcpu->syncp); in gnet_stats_add_basic_cpu()139 bytes = u64_stats_read(&bcpu->bytes); in gnet_stats_add_basic_cpu()140 packets = u64_stats_read(&bcpu->packets); in gnet_stats_add_basic_cpu()141 } while (u64_stats_fetch_retry_irq(&bcpu->syncp, start)); in gnet_stats_add_basic_cpu()185 struct gnet_stats_basic_sync *bcpu = per_cpu_ptr(cpu, i); in gnet_stats_read_basic() local190 start = u64_stats_fetch_begin_irq(&bcpu->syncp); in gnet_stats_read_basic()191 bytes = u64_stats_read(&bcpu->bytes); in gnet_stats_read_basic()192 packets = u64_stats_read(&bcpu->packets); in gnet_stats_read_basic()193 } while (u64_stats_fetch_retry_irq(&bcpu->syncp, start)); in gnet_stats_read_basic()
64 register int bcpu = boot_cpuid; in titan_update_irq_hw() local78 if (bcpu == 0) mask0 |= isa_enable; in titan_update_irq_hw()79 else if (bcpu == 1) mask1 |= isa_enable; in titan_update_irq_hw()80 else if (bcpu == 2) mask2 |= isa_enable; in titan_update_irq_hw()104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
51 register int bcpu = boot_cpuid; in tsunami_update_irq_hw() local63 if (bcpu == 0) mask0 |= isa_enable; in tsunami_update_irq_hw()64 else if (bcpu == 1) mask1 |= isa_enable; in tsunami_update_irq_hw()65 else if (bcpu == 2) mask2 |= isa_enable; in tsunami_update_irq_hw()88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()