Searched refs:aud_pll_ctrl0 (Results 1 – 1 of 1) sorted by relevance
72 u32 aud_pll_ctrl0; member120 u32 aud_pll_ctrl0; in audio_pll_recalc_rate() local123 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()124 aud_pll_ctrl0 &= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK | in audio_pll_recalc_rate()148 if (val != aud_pll_ctrl0) in audio_pll_recalc_rate()401 priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in mmp2_audio_clk_suspend()414 writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in mmp2_audio_clk_resume()