1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
35
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
38
39 #define PCI_REVISION_ID_HIP08 0x21
40 #define PCI_REVISION_ID_HIP09 0x30
41
42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
43
44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
45
46 #define BA_BYTE_LEN 8
47
48 #define HNS_ROCE_MIN_CQE_NUM 0x40
49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
50
51 #define HNS_ROCE_MAX_IRQ_NUM 128
52
53 #define HNS_ROCE_SGE_IN_WQE 2
54 #define HNS_ROCE_SGE_SHIFT 4
55
56 #define EQ_ENABLE 1
57 #define EQ_DISABLE 0
58
59 #define HNS_ROCE_CEQ 0
60 #define HNS_ROCE_AEQ 1
61
62 #define HNS_ROCE_CEQE_SIZE 0x4
63 #define HNS_ROCE_AEQE_SIZE 0x10
64
65 #define HNS_ROCE_V3_EQE_SIZE 0x40
66
67 #define HNS_ROCE_V2_CQE_SIZE 32
68 #define HNS_ROCE_V3_CQE_SIZE 64
69
70 #define HNS_ROCE_V2_QPC_SZ 256
71 #define HNS_ROCE_V3_QPC_SZ 512
72
73 #define HNS_ROCE_MAX_PORTS 6
74 #define HNS_ROCE_GID_SIZE 16
75 #define HNS_ROCE_SGE_SIZE 16
76 #define HNS_ROCE_DWQE_SIZE 65536
77
78 #define HNS_ROCE_HOP_NUM_0 0xff
79
80 #define MR_TYPE_MR 0x00
81 #define MR_TYPE_FRMR 0x01
82 #define MR_TYPE_DMA 0x03
83
84 #define HNS_ROCE_FRMR_MAX_PA 512
85
86 #define PKEY_ID 0xffff
87 #define NODE_DESC_SIZE 64
88 #define DB_REG_OFFSET 0x1000
89
90 /* Configure to HW for PAGE_SIZE larger than 4KB */
91 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
92
93 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
94 #define SRQ_DB_REG 0x230
95
96 #define HNS_ROCE_QP_BANK_NUM 8
97 #define HNS_ROCE_CQ_BANK_NUM 4
98
99 #define CQ_BANKID_SHIFT 2
100
101 enum {
102 SERV_TYPE_RC,
103 SERV_TYPE_UC,
104 SERV_TYPE_RD,
105 SERV_TYPE_UD,
106 SERV_TYPE_XRC = 5,
107 };
108
109 enum hns_roce_event {
110 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
111 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
112 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
113 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
114 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
115 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
116 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
117 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
118 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
119 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
120 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
121 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
122 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
123 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
124 /* 0x10 and 0x11 is unused in currently application case */
125 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
126 HNS_ROCE_EVENT_TYPE_MB = 0x13,
127 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
128 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
129 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
130 };
131
132 enum {
133 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
134 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
135 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
136 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
137 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
138 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
139 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
140 HNS_ROCE_CAP_FLAG_MW = BIT(7),
141 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
142 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
143 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
144 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12),
145 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
146 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
147 };
148
149 #define HNS_ROCE_DB_TYPE_COUNT 2
150 #define HNS_ROCE_DB_UNIT_SIZE 4
151
152 enum {
153 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
154 };
155
156 enum hns_roce_reset_stage {
157 HNS_ROCE_STATE_NON_RST,
158 HNS_ROCE_STATE_RST_BEF_DOWN,
159 HNS_ROCE_STATE_RST_DOWN,
160 HNS_ROCE_STATE_RST_UNINIT,
161 HNS_ROCE_STATE_RST_INIT,
162 HNS_ROCE_STATE_RST_INITED,
163 };
164
165 enum hns_roce_instance_state {
166 HNS_ROCE_STATE_NON_INIT,
167 HNS_ROCE_STATE_INIT,
168 HNS_ROCE_STATE_INITED,
169 HNS_ROCE_STATE_UNINIT,
170 };
171
172 enum {
173 HNS_ROCE_RST_DIRECT_RETURN = 0,
174 };
175
176 #define HNS_ROCE_CMD_SUCCESS 1
177
178 /* The minimum page size is 4K for hardware */
179 #define HNS_HW_PAGE_SHIFT 12
180 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
181
182 struct hns_roce_uar {
183 u64 pfn;
184 unsigned long index;
185 unsigned long logic_idx;
186 };
187
188 enum hns_roce_mmap_type {
189 HNS_ROCE_MMAP_TYPE_DB = 1,
190 HNS_ROCE_MMAP_TYPE_DWQE,
191 };
192
193 struct hns_user_mmap_entry {
194 struct rdma_user_mmap_entry rdma_entry;
195 enum hns_roce_mmap_type mmap_type;
196 u64 address;
197 };
198
199 struct hns_roce_ucontext {
200 struct ib_ucontext ibucontext;
201 struct hns_roce_uar uar;
202 struct list_head page_list;
203 struct mutex page_mutex;
204 struct hns_user_mmap_entry *db_mmap_entry;
205 };
206
207 struct hns_roce_pd {
208 struct ib_pd ibpd;
209 unsigned long pdn;
210 };
211
212 struct hns_roce_xrcd {
213 struct ib_xrcd ibxrcd;
214 u32 xrcdn;
215 };
216
217 struct hns_roce_bitmap {
218 /* Bitmap Traversal last a bit which is 1 */
219 unsigned long last;
220 unsigned long top;
221 unsigned long max;
222 unsigned long reserved_top;
223 unsigned long mask;
224 spinlock_t lock;
225 unsigned long *table;
226 };
227
228 struct hns_roce_ida {
229 struct ida ida;
230 u32 min; /* Lowest ID to allocate. */
231 u32 max; /* Highest ID to allocate. */
232 };
233
234 /* For Hardware Entry Memory */
235 struct hns_roce_hem_table {
236 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
237 u32 type;
238 /* HEM array elment num */
239 unsigned long num_hem;
240 /* Single obj size */
241 unsigned long obj_size;
242 unsigned long table_chunk_size;
243 int lowmem;
244 struct mutex mutex;
245 struct hns_roce_hem **hem;
246 u64 **bt_l1;
247 dma_addr_t *bt_l1_dma_addr;
248 u64 **bt_l0;
249 dma_addr_t *bt_l0_dma_addr;
250 };
251
252 struct hns_roce_buf_region {
253 u32 offset; /* page offset */
254 u32 count; /* page count */
255 int hopnum; /* addressing hop num */
256 };
257
258 #define HNS_ROCE_MAX_BT_REGION 3
259 #define HNS_ROCE_MAX_BT_LEVEL 3
260 struct hns_roce_hem_list {
261 struct list_head root_bt;
262 /* link all bt dma mem by hop config */
263 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
264 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
265 dma_addr_t root_ba; /* pointer to the root ba table */
266 };
267
268 struct hns_roce_buf_attr {
269 struct {
270 size_t size; /* region size */
271 int hopnum; /* multi-hop addressing hop num */
272 } region[HNS_ROCE_MAX_BT_REGION];
273 unsigned int region_count; /* valid region count */
274 unsigned int page_shift; /* buffer page shift */
275 unsigned int user_access; /* umem access flag */
276 bool mtt_only; /* only alloc buffer-required MTT memory */
277 };
278
279 struct hns_roce_hem_cfg {
280 dma_addr_t root_ba; /* root BA table's address */
281 bool is_direct; /* addressing without BA table */
282 unsigned int ba_pg_shift; /* BA table page shift */
283 unsigned int buf_pg_shift; /* buffer page shift */
284 unsigned int buf_pg_count; /* buffer page count */
285 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
286 unsigned int region_count;
287 };
288
289 /* memory translate region */
290 struct hns_roce_mtr {
291 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
292 struct ib_umem *umem; /* user space buffer */
293 struct hns_roce_buf *kmem; /* kernel space buffer */
294 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
295 };
296
297 struct hns_roce_mw {
298 struct ib_mw ibmw;
299 u32 pdn;
300 u32 rkey;
301 int enabled; /* MW's active status */
302 u32 pbl_hop_num;
303 u32 pbl_ba_pg_sz;
304 u32 pbl_buf_pg_sz;
305 };
306
307 struct hns_roce_mr {
308 struct ib_mr ibmr;
309 u64 iova; /* MR's virtual original addr */
310 u64 size; /* Address range of MR */
311 u32 key; /* Key of MR */
312 u32 pd; /* PD num of MR */
313 u32 access; /* Access permission of MR */
314 int enabled; /* MR's active status */
315 int type; /* MR's register type */
316 u32 pbl_hop_num; /* multi-hop number */
317 struct hns_roce_mtr pbl_mtr;
318 u32 npages;
319 dma_addr_t *page_list;
320 };
321
322 struct hns_roce_mr_table {
323 struct hns_roce_ida mtpt_ida;
324 struct hns_roce_hem_table mtpt_table;
325 };
326
327 struct hns_roce_wq {
328 u64 *wrid; /* Work request ID */
329 spinlock_t lock;
330 u32 wqe_cnt; /* WQE num */
331 u32 max_gs;
332 u32 rsv_sge;
333 u32 offset;
334 u32 wqe_shift; /* WQE size */
335 u32 head;
336 u32 tail;
337 void __iomem *db_reg;
338 };
339
340 struct hns_roce_sge {
341 unsigned int sge_cnt; /* SGE num */
342 u32 offset;
343 u32 sge_shift; /* SGE size */
344 };
345
346 struct hns_roce_buf_list {
347 void *buf;
348 dma_addr_t map;
349 };
350
351 /*
352 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
353 * dma address range.
354 *
355 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
356 *
357 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
358 * the allocated size is smaller than the required size.
359 */
360 enum {
361 HNS_ROCE_BUF_DIRECT = BIT(0),
362 HNS_ROCE_BUF_NOSLEEP = BIT(1),
363 HNS_ROCE_BUF_NOFAIL = BIT(2),
364 };
365
366 struct hns_roce_buf {
367 struct hns_roce_buf_list *trunk_list;
368 u32 ntrunks;
369 u32 npages;
370 unsigned int trunk_shift;
371 unsigned int page_shift;
372 };
373
374 struct hns_roce_db_pgdir {
375 struct list_head list;
376 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
377 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
378 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
379 u32 *page;
380 dma_addr_t db_dma;
381 };
382
383 struct hns_roce_user_db_page {
384 struct list_head list;
385 struct ib_umem *umem;
386 unsigned long user_virt;
387 refcount_t refcount;
388 };
389
390 struct hns_roce_db {
391 u32 *db_record;
392 union {
393 struct hns_roce_db_pgdir *pgdir;
394 struct hns_roce_user_db_page *user_page;
395 } u;
396 dma_addr_t dma;
397 void *virt_addr;
398 unsigned long index;
399 unsigned long order;
400 };
401
402 struct hns_roce_cq {
403 struct ib_cq ib_cq;
404 struct hns_roce_mtr mtr;
405 struct hns_roce_db db;
406 u32 flags;
407 spinlock_t lock;
408 u32 cq_depth;
409 u32 cons_index;
410 u32 *set_ci_db;
411 void __iomem *db_reg;
412 int arm_sn;
413 int cqe_size;
414 unsigned long cqn;
415 u32 vector;
416 refcount_t refcount;
417 struct completion free;
418 struct list_head sq_list; /* all qps on this send cq */
419 struct list_head rq_list; /* all qps on this recv cq */
420 int is_armed; /* cq is armed */
421 struct list_head node; /* all armed cqs are on a list */
422 };
423
424 struct hns_roce_idx_que {
425 struct hns_roce_mtr mtr;
426 u32 entry_shift;
427 unsigned long *bitmap;
428 u32 head;
429 u32 tail;
430 };
431
432 struct hns_roce_srq {
433 struct ib_srq ibsrq;
434 unsigned long srqn;
435 u32 wqe_cnt;
436 int max_gs;
437 u32 rsv_sge;
438 u32 wqe_shift;
439 u32 cqn;
440 u32 xrcdn;
441 void __iomem *db_reg;
442
443 refcount_t refcount;
444 struct completion free;
445
446 struct hns_roce_mtr buf_mtr;
447
448 u64 *wrid;
449 struct hns_roce_idx_que idx_que;
450 spinlock_t lock;
451 struct mutex mutex;
452 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
453 };
454
455 struct hns_roce_uar_table {
456 struct hns_roce_bitmap bitmap;
457 };
458
459 struct hns_roce_bank {
460 struct ida ida;
461 u32 inuse; /* Number of IDs allocated */
462 u32 min; /* Lowest ID to allocate. */
463 u32 max; /* Highest ID to allocate. */
464 u32 next; /* Next ID to allocate. */
465 };
466
467 struct hns_roce_idx_table {
468 u32 *spare_idx;
469 u32 head;
470 u32 tail;
471 };
472
473 struct hns_roce_qp_table {
474 struct hns_roce_hem_table qp_table;
475 struct hns_roce_hem_table irrl_table;
476 struct hns_roce_hem_table trrl_table;
477 struct hns_roce_hem_table sccc_table;
478 struct mutex scc_mutex;
479 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
480 struct mutex bank_mutex;
481 struct hns_roce_idx_table idx_table;
482 };
483
484 struct hns_roce_cq_table {
485 struct xarray array;
486 struct hns_roce_hem_table table;
487 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
488 struct mutex bank_mutex;
489 };
490
491 struct hns_roce_srq_table {
492 struct hns_roce_ida srq_ida;
493 struct xarray xa;
494 struct hns_roce_hem_table table;
495 };
496
497 struct hns_roce_av {
498 u8 port;
499 u8 gid_index;
500 u8 stat_rate;
501 u8 hop_limit;
502 u32 flowlabel;
503 u16 udp_sport;
504 u8 sl;
505 u8 tclass;
506 u8 dgid[HNS_ROCE_GID_SIZE];
507 u8 mac[ETH_ALEN];
508 u16 vlan_id;
509 u8 vlan_en;
510 };
511
512 struct hns_roce_ah {
513 struct ib_ah ibah;
514 struct hns_roce_av av;
515 };
516
517 struct hns_roce_cmd_context {
518 struct completion done;
519 int result;
520 int next;
521 u64 out_param;
522 u16 token;
523 u16 busy;
524 };
525
526 enum hns_roce_cmdq_state {
527 HNS_ROCE_CMDQ_STATE_NORMAL,
528 HNS_ROCE_CMDQ_STATE_FATAL_ERR,
529 };
530
531 struct hns_roce_cmdq {
532 struct dma_pool *pool;
533 struct semaphore poll_sem;
534 /*
535 * Event mode: cmd register mutex protection,
536 * ensure to not exceed max_cmds and user use limit region
537 */
538 struct semaphore event_sem;
539 int max_cmds;
540 spinlock_t context_lock;
541 int free_head;
542 struct hns_roce_cmd_context *context;
543 /*
544 * Process whether use event mode, init default non-zero
545 * After the event queue of cmd event ready,
546 * can switch into event mode
547 * close device, switch into poll mode(non event mode)
548 */
549 u8 use_events;
550 enum hns_roce_cmdq_state state;
551 };
552
553 struct hns_roce_cmd_mailbox {
554 void *buf;
555 dma_addr_t dma;
556 };
557
558 struct hns_roce_mbox_msg {
559 u64 in_param;
560 u64 out_param;
561 u8 cmd;
562 u32 tag;
563 u16 token;
564 u8 event_en;
565 };
566
567 struct hns_roce_dev;
568
569 struct hns_roce_rinl_sge {
570 void *addr;
571 u32 len;
572 };
573
574 struct hns_roce_rinl_wqe {
575 struct hns_roce_rinl_sge *sg_list;
576 u32 sge_cnt;
577 };
578
579 struct hns_roce_rinl_buf {
580 struct hns_roce_rinl_wqe *wqe_list;
581 u32 wqe_cnt;
582 };
583
584 enum {
585 HNS_ROCE_FLUSH_FLAG = 0,
586 };
587
588 struct hns_roce_work {
589 struct hns_roce_dev *hr_dev;
590 struct work_struct work;
591 int event_type;
592 int sub_type;
593 u32 queue_num;
594 };
595
596 struct hns_roce_qp {
597 struct ib_qp ibqp;
598 struct hns_roce_wq rq;
599 struct hns_roce_db rdb;
600 struct hns_roce_db sdb;
601 unsigned long en_flags;
602 u32 doorbell_qpn;
603 enum ib_sig_type sq_signal_bits;
604 struct hns_roce_wq sq;
605
606 struct hns_roce_mtr mtr;
607
608 u32 buff_size;
609 struct mutex mutex;
610 u8 port;
611 u8 phy_port;
612 u8 sl;
613 u8 resp_depth;
614 u8 state;
615 u32 atomic_rd_en;
616 u32 qkey;
617 void (*event)(struct hns_roce_qp *qp,
618 enum hns_roce_event event_type);
619 unsigned long qpn;
620
621 u32 xrcdn;
622
623 refcount_t refcount;
624 struct completion free;
625
626 struct hns_roce_sge sge;
627 u32 next_sge;
628 enum ib_mtu path_mtu;
629 u32 max_inline_data;
630 u8 free_mr_en;
631
632 /* 0: flush needed, 1: unneeded */
633 unsigned long flush_flag;
634 struct hns_roce_work flush_work;
635 struct hns_roce_rinl_buf rq_inl_buf;
636 struct list_head node; /* all qps are on a list */
637 struct list_head rq_node; /* all recv qps are on a list */
638 struct list_head sq_node; /* all send qps are on a list */
639 struct hns_user_mmap_entry *dwqe_mmap_entry;
640 };
641
642 struct hns_roce_ib_iboe {
643 spinlock_t lock;
644 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
645 struct notifier_block nb;
646 u8 phy_port[HNS_ROCE_MAX_PORTS];
647 };
648
649 struct hns_roce_ceqe {
650 __le32 comp;
651 __le32 rsv[15];
652 };
653
654 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l)
655
656 #define CEQE_CQN CEQE_FIELD_LOC(23, 0)
657 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31)
658
659 struct hns_roce_aeqe {
660 __le32 asyn;
661 union {
662 struct {
663 __le32 num;
664 u32 rsv0;
665 u32 rsv1;
666 } queue_event;
667
668 struct {
669 __le64 out_param;
670 __le16 token;
671 u8 status;
672 u8 rsv0;
673 } __packed cmd;
674 } event;
675 __le32 rsv[12];
676 };
677
678 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l)
679
680 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0)
681 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8)
682 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31)
683 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32)
684
685 struct hns_roce_eq {
686 struct hns_roce_dev *hr_dev;
687 void __iomem *db_reg;
688
689 int type_flag; /* Aeq:1 ceq:0 */
690 int eqn;
691 u32 entries;
692 int eqe_size;
693 int irq;
694 u32 cons_index;
695 int over_ignore;
696 int coalesce;
697 int arm_st;
698 int hop_num;
699 struct hns_roce_mtr mtr;
700 u16 eq_max_cnt;
701 u32 eq_period;
702 int shift;
703 int event_type;
704 int sub_type;
705 };
706
707 struct hns_roce_eq_table {
708 struct hns_roce_eq *eq;
709 };
710
711 enum cong_type {
712 CONG_TYPE_DCQCN,
713 CONG_TYPE_LDCP,
714 CONG_TYPE_HC3,
715 CONG_TYPE_DIP,
716 };
717
718 struct hns_roce_caps {
719 u64 fw_ver;
720 u8 num_ports;
721 int gid_table_len[HNS_ROCE_MAX_PORTS];
722 int pkey_table_len[HNS_ROCE_MAX_PORTS];
723 int local_ca_ack_delay;
724 int num_uars;
725 u32 phy_num_uars;
726 u32 max_sq_sg;
727 u32 max_sq_inline;
728 u32 max_rq_sg;
729 u32 max_extend_sg;
730 u32 num_qps;
731 u32 num_pi_qps;
732 u32 reserved_qps;
733 u32 num_srqs;
734 u32 max_wqes;
735 u32 max_srq_wrs;
736 u32 max_srq_sges;
737 u32 max_sq_desc_sz;
738 u32 max_rq_desc_sz;
739 u32 max_srq_desc_sz;
740 int max_qp_init_rdma;
741 int max_qp_dest_rdma;
742 u32 num_cqs;
743 u32 max_cqes;
744 u32 min_cqes;
745 u32 min_wqes;
746 u32 reserved_cqs;
747 u32 reserved_srqs;
748 int num_aeq_vectors;
749 int num_comp_vectors;
750 int num_other_vectors;
751 u32 num_mtpts;
752 u32 num_mtt_segs;
753 u32 num_srqwqe_segs;
754 u32 num_idx_segs;
755 int reserved_mrws;
756 int reserved_uars;
757 int num_pds;
758 int reserved_pds;
759 u32 num_xrcds;
760 u32 reserved_xrcds;
761 u32 mtt_entry_sz;
762 u32 cqe_sz;
763 u32 page_size_cap;
764 u32 reserved_lkey;
765 int mtpt_entry_sz;
766 int qpc_sz;
767 int irrl_entry_sz;
768 int trrl_entry_sz;
769 int cqc_entry_sz;
770 int sccc_sz;
771 int qpc_timer_entry_sz;
772 int cqc_timer_entry_sz;
773 int srqc_entry_sz;
774 int idx_entry_sz;
775 u32 pbl_ba_pg_sz;
776 u32 pbl_buf_pg_sz;
777 u32 pbl_hop_num;
778 int aeqe_depth;
779 int ceqe_depth;
780 u32 aeqe_size;
781 u32 ceqe_size;
782 enum ib_mtu max_mtu;
783 u32 qpc_bt_num;
784 u32 qpc_timer_bt_num;
785 u32 srqc_bt_num;
786 u32 cqc_bt_num;
787 u32 cqc_timer_bt_num;
788 u32 mpt_bt_num;
789 u32 eqc_bt_num;
790 u32 smac_bt_num;
791 u32 sgid_bt_num;
792 u32 sccc_bt_num;
793 u32 gmv_bt_num;
794 u32 qpc_ba_pg_sz;
795 u32 qpc_buf_pg_sz;
796 u32 qpc_hop_num;
797 u32 srqc_ba_pg_sz;
798 u32 srqc_buf_pg_sz;
799 u32 srqc_hop_num;
800 u32 cqc_ba_pg_sz;
801 u32 cqc_buf_pg_sz;
802 u32 cqc_hop_num;
803 u32 mpt_ba_pg_sz;
804 u32 mpt_buf_pg_sz;
805 u32 mpt_hop_num;
806 u32 mtt_ba_pg_sz;
807 u32 mtt_buf_pg_sz;
808 u32 mtt_hop_num;
809 u32 wqe_sq_hop_num;
810 u32 wqe_sge_hop_num;
811 u32 wqe_rq_hop_num;
812 u32 sccc_ba_pg_sz;
813 u32 sccc_buf_pg_sz;
814 u32 sccc_hop_num;
815 u32 qpc_timer_ba_pg_sz;
816 u32 qpc_timer_buf_pg_sz;
817 u32 qpc_timer_hop_num;
818 u32 cqc_timer_ba_pg_sz;
819 u32 cqc_timer_buf_pg_sz;
820 u32 cqc_timer_hop_num;
821 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
822 u32 cqe_buf_pg_sz;
823 u32 cqe_hop_num;
824 u32 srqwqe_ba_pg_sz;
825 u32 srqwqe_buf_pg_sz;
826 u32 srqwqe_hop_num;
827 u32 idx_ba_pg_sz;
828 u32 idx_buf_pg_sz;
829 u32 idx_hop_num;
830 u32 eqe_ba_pg_sz;
831 u32 eqe_buf_pg_sz;
832 u32 eqe_hop_num;
833 u32 gmv_entry_num;
834 u32 gmv_entry_sz;
835 u32 gmv_ba_pg_sz;
836 u32 gmv_buf_pg_sz;
837 u32 gmv_hop_num;
838 u32 sl_num;
839 u32 llm_buf_pg_sz;
840 u32 chunk_sz; /* chunk size in non multihop mode */
841 u64 flags;
842 u16 default_ceq_max_cnt;
843 u16 default_ceq_period;
844 u16 default_aeq_max_cnt;
845 u16 default_aeq_period;
846 u16 default_aeq_arm_st;
847 u16 default_ceq_arm_st;
848 enum cong_type cong_type;
849 };
850
851 struct hns_roce_dfx_hw {
852 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
853 int *buffer);
854 };
855
856 enum hns_roce_device_state {
857 HNS_ROCE_DEVICE_STATE_INITED,
858 HNS_ROCE_DEVICE_STATE_RST_DOWN,
859 HNS_ROCE_DEVICE_STATE_UNINIT,
860 };
861
862 struct hns_roce_hw {
863 int (*cmq_init)(struct hns_roce_dev *hr_dev);
864 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
865 int (*hw_profile)(struct hns_roce_dev *hr_dev);
866 int (*hw_init)(struct hns_roce_dev *hr_dev);
867 void (*hw_exit)(struct hns_roce_dev *hr_dev);
868 int (*post_mbox)(struct hns_roce_dev *hr_dev,
869 struct hns_roce_mbox_msg *mbox_msg);
870 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev);
871 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
872 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index,
873 const union ib_gid *gid, const struct ib_gid_attr *attr);
874 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port,
875 const u8 *addr);
876 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
877 struct hns_roce_mr *mr);
878 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
879 struct hns_roce_mr *mr, int flags,
880 void *mb_buf);
881 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
882 struct hns_roce_mr *mr);
883 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
884 void (*write_cqc)(struct hns_roce_dev *hr_dev,
885 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
886 dma_addr_t dma_handle);
887 int (*set_hem)(struct hns_roce_dev *hr_dev,
888 struct hns_roce_hem_table *table, int obj, u32 step_idx);
889 int (*clear_hem)(struct hns_roce_dev *hr_dev,
890 struct hns_roce_hem_table *table, int obj,
891 u32 step_idx);
892 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
893 int attr_mask, enum ib_qp_state cur_state,
894 enum ib_qp_state new_state);
895 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
896 struct hns_roce_qp *hr_qp);
897 void (*dereg_mr)(struct hns_roce_dev *hr_dev);
898 int (*init_eq)(struct hns_roce_dev *hr_dev);
899 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
900 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
901 const struct ib_device_ops *hns_roce_dev_ops;
902 const struct ib_device_ops *hns_roce_dev_srq_ops;
903 };
904
905 struct hns_roce_dev {
906 struct ib_device ib_dev;
907 struct pci_dev *pci_dev;
908 struct device *dev;
909 struct hns_roce_uar priv_uar;
910 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
911 spinlock_t sm_lock;
912 bool active;
913 bool is_reset;
914 bool dis_db;
915 unsigned long reset_cnt;
916 struct hns_roce_ib_iboe iboe;
917 enum hns_roce_device_state state;
918 struct list_head qp_list; /* list of all qps on this dev */
919 spinlock_t qp_list_lock; /* protect qp_list */
920 struct list_head dip_list; /* list of all dest ips on this dev */
921 spinlock_t dip_list_lock; /* protect dip_list */
922
923 struct list_head pgdir_list;
924 struct mutex pgdir_mutex;
925 int irq[HNS_ROCE_MAX_IRQ_NUM];
926 u8 __iomem *reg_base;
927 void __iomem *mem_base;
928 struct hns_roce_caps caps;
929 struct xarray qp_table_xa;
930
931 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
932 u64 sys_image_guid;
933 u32 vendor_id;
934 u32 vendor_part_id;
935 u32 hw_rev;
936 void __iomem *priv_addr;
937
938 struct hns_roce_cmdq cmd;
939 struct hns_roce_ida pd_ida;
940 struct hns_roce_ida xrcd_ida;
941 struct hns_roce_ida uar_ida;
942 struct hns_roce_mr_table mr_table;
943 struct hns_roce_cq_table cq_table;
944 struct hns_roce_srq_table srq_table;
945 struct hns_roce_qp_table qp_table;
946 struct hns_roce_eq_table eq_table;
947 struct hns_roce_hem_table qpc_timer_table;
948 struct hns_roce_hem_table cqc_timer_table;
949 /* GMV is the memory area that the driver allocates for the hardware
950 * to store SGID, SMAC and VLAN information.
951 */
952 struct hns_roce_hem_table gmv_table;
953
954 int cmd_mod;
955 int loop_idc;
956 u32 sdb_offset;
957 u32 odb_offset;
958 const struct hns_roce_hw *hw;
959 void *priv;
960 struct workqueue_struct *irq_workq;
961 const struct hns_roce_dfx_hw *dfx;
962 u32 func_num;
963 u32 is_vf;
964 u32 cong_algo_tmpl_id;
965 u64 dwqe_page;
966 };
967
to_hr_dev(struct ib_device * ib_dev)968 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
969 {
970 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
971 }
972
973 static inline struct hns_roce_ucontext
to_hr_ucontext(struct ib_ucontext * ibucontext)974 *to_hr_ucontext(struct ib_ucontext *ibucontext)
975 {
976 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
977 }
978
to_hr_pd(struct ib_pd * ibpd)979 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
980 {
981 return container_of(ibpd, struct hns_roce_pd, ibpd);
982 }
983
to_hr_xrcd(struct ib_xrcd * ibxrcd)984 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
985 {
986 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
987 }
988
to_hr_ah(struct ib_ah * ibah)989 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
990 {
991 return container_of(ibah, struct hns_roce_ah, ibah);
992 }
993
to_hr_mr(struct ib_mr * ibmr)994 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
995 {
996 return container_of(ibmr, struct hns_roce_mr, ibmr);
997 }
998
to_hr_mw(struct ib_mw * ibmw)999 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1000 {
1001 return container_of(ibmw, struct hns_roce_mw, ibmw);
1002 }
1003
to_hr_qp(struct ib_qp * ibqp)1004 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1005 {
1006 return container_of(ibqp, struct hns_roce_qp, ibqp);
1007 }
1008
to_hr_cq(struct ib_cq * ib_cq)1009 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1010 {
1011 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1012 }
1013
to_hr_srq(struct ib_srq * ibsrq)1014 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1015 {
1016 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1017 }
1018
1019 static inline struct hns_user_mmap_entry *
to_hns_mmap(struct rdma_user_mmap_entry * rdma_entry)1020 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry)
1021 {
1022 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry);
1023 }
1024
hns_roce_write64_k(__le32 val[2],void __iomem * dest)1025 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1026 {
1027 writeq(*(u64 *)val, dest);
1028 }
1029
1030 static inline struct hns_roce_qp
__hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1031 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1032 {
1033 return xa_load(&hr_dev->qp_table_xa, qpn);
1034 }
1035
hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1036 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1037 unsigned int offset)
1038 {
1039 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1040 (offset & ((1 << buf->trunk_shift) - 1));
1041 }
1042
hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1043 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1044 unsigned int offset)
1045 {
1046 return buf->trunk_list[offset >> buf->trunk_shift].map +
1047 (offset & ((1 << buf->trunk_shift) - 1));
1048 }
1049
hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1050 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1051 {
1052 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1053 }
1054
1055 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1056
to_hr_hw_page_addr(u64 addr)1057 static inline u64 to_hr_hw_page_addr(u64 addr)
1058 {
1059 return addr >> HNS_HW_PAGE_SHIFT;
1060 }
1061
to_hr_hw_page_shift(u32 page_shift)1062 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1063 {
1064 return page_shift - HNS_HW_PAGE_SHIFT;
1065 }
1066
to_hr_hem_hopnum(u32 hopnum,u32 count)1067 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1068 {
1069 if (count > 0)
1070 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1071
1072 return 0;
1073 }
1074
to_hr_hem_entries_size(u32 count,u32 buf_shift)1075 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1076 {
1077 return hr_hw_page_align(count << buf_shift);
1078 }
1079
to_hr_hem_entries_count(u32 count,u32 buf_shift)1080 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1081 {
1082 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1083 }
1084
to_hr_hem_entries_shift(u32 count,u32 buf_shift)1085 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1086 {
1087 if (!count)
1088 return 0;
1089
1090 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1091 }
1092
1093 #define DSCP_SHIFT 2
1094
get_tclass(const struct ib_global_route * grh)1095 static inline u8 get_tclass(const struct ib_global_route *grh)
1096 {
1097 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1098 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1099 }
1100
1101 void hns_roce_init_uar_table(struct hns_roce_dev *dev);
1102 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1103
1104 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1105 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1106 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1107 u64 out_param);
1108 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1109 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1110
1111 /* hns roce hw need current block and next block addr from mtt */
1112 #define MTT_MIN_COUNT 2
1113 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1114 u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1115 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1116 struct hns_roce_buf_attr *buf_attr,
1117 unsigned int page_shift, struct ib_udata *udata,
1118 unsigned long user_addr);
1119 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1120 struct hns_roce_mtr *mtr);
1121 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1122 dma_addr_t *pages, unsigned int page_cnt);
1123
1124 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1125 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1126 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1127 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1128 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1129 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1130
1131 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1132 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1133 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1134
1135 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1136
1137 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1138 struct ib_udata *udata);
1139 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1140 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1141 {
1142 return 0;
1143 }
1144
1145 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1146 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1147
1148 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1149 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1150 u64 virt_addr, int access_flags,
1151 struct ib_udata *udata);
1152 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1153 u64 length, u64 virt_addr,
1154 int mr_access_flags, struct ib_pd *pd,
1155 struct ib_udata *udata);
1156 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1157 u32 max_num_sg);
1158 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1159 unsigned int *sg_offset);
1160 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1161 unsigned long key_to_hw_index(u32 key);
1162
1163 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1164 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1165
1166 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1167 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1168 u32 page_shift, u32 flags);
1169
1170 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1171 int buf_cnt, struct hns_roce_buf *buf,
1172 unsigned int page_shift);
1173 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1174 int buf_cnt, struct ib_umem *umem,
1175 unsigned int page_shift);
1176
1177 int hns_roce_create_srq(struct ib_srq *srq,
1178 struct ib_srq_init_attr *srq_init_attr,
1179 struct ib_udata *udata);
1180 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1181 enum ib_srq_attr_mask srq_attr_mask,
1182 struct ib_udata *udata);
1183 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1184
1185 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1186 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1187
1188 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr,
1189 struct ib_udata *udata);
1190 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1191 int attr_mask, struct ib_udata *udata);
1192 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1193 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1194 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1195 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1196 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1197 struct ib_cq *ib_cq);
1198 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1199 struct hns_roce_cq *recv_cq);
1200 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1201 struct hns_roce_cq *recv_cq);
1202 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1203 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1204 struct ib_udata *udata);
1205 __be32 send_ieth(const struct ib_send_wr *wr);
1206 int to_hr_qp_type(int qp_type);
1207
1208 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1209 struct ib_udata *udata);
1210
1211 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1212 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1213 struct hns_roce_db *db);
1214 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1215 struct hns_roce_db *db);
1216 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1217 int order);
1218 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1219
1220 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1221 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1222 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1223 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1224 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1225 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1226 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1227 int hns_roce_init(struct hns_roce_dev *hr_dev);
1228 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1229 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1230 struct ib_cq *ib_cq);
1231 struct hns_user_mmap_entry *
1232 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
1233 size_t length,
1234 enum hns_roce_mmap_type mmap_type);
1235 #endif /* _HNS_ROCE_DEVICE_H */
1236