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/linux-5.19.10/Documentation/devicetree/bindings/clock/ti/
Dapll.txt17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
34 compatible = "ti,dra7-apll-clock";
39 compatible = "ti,omap2-apll-clock";
/linux-5.19.10/Documentation/devicetree/bindings/clock/
Dimx7ulp-pcc-clock.yaml54 - description: apll pfd2
55 - description: apll pfd1
56 - description: apll pfd0
/linux-5.19.10/sound/soc/mediatek/mt8183/
Dmt8183-afe-clk.h32 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
Dmt8183-dai-tdm.c440 int apll; in mtk_dai_tdm_cal_mclk() local
443 apll = mt8183_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
444 apll_rate = mt8183_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
459 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
Dmt8183-afe-clk.c487 int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8183_get_apll_rate() argument
489 return (apll == MT8183_APLL1) ? 180633600 : 196608000; in mt8183_get_apll_rate()
545 int apll = mt8183_get_apll_by_rate(afe, rate); in mt8183_mck_enable() local
546 int apll_clk_id = apll == MT8183_APLL1 ? in mt8183_mck_enable()
Dmt8183-dai-i2s.c801 int apll; in mtk_dai_i2s_set_sysclk() local
816 apll = mt8183_get_apll_by_rate(afe, freq); in mtk_dai_i2s_set_sysclk()
817 apll_rate = mt8183_get_apll_rate(afe, apll); in mtk_dai_i2s_set_sysclk()
831 i2s_priv->mclk_apll = apll; in mtk_dai_i2s_set_sysclk()
/linux-5.19.10/sound/soc/mediatek/mt8192/
Dmt8192-dai-tdm.c489 int apll; in mtk_dai_tdm_cal_mclk() local
492 apll = mt8192_get_apll_by_rate(afe, freq); in mtk_dai_tdm_cal_mclk()
493 apll_rate = mt8192_get_apll_rate(afe, apll); in mtk_dai_tdm_cal_mclk()
508 tdm_priv->mclk_apll = apll; in mtk_dai_tdm_cal_mclk()
Dmt8192-afe-clk.c389 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8192_get_apll_rate() argument
391 return (apll == MT8192_APLL1) ? 180633600 : 196608000; in mt8192_get_apll_rate()
569 int apll = mt8192_get_apll_by_rate(afe, rate); in mt8192_mck_enable() local
570 int apll_clk_id = apll == MT8192_APLL1 ? in mt8192_mck_enable()
Dmt8192-afe-clk.h233 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll);
/linux-5.19.10/drivers/clk/samsung/
Dclk-exynos5250.c105 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
733 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
749 #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \ argument
750 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
811 exynos5250_plls[apll].rate_table = apll_24mhz_tbl; in exynos5250_clk_init()
Dclk-exynos4.c146 apll, mpll, epll, vpll, enumerator
1147 [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1158 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1192 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ argument
1193 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1268 exynos4210_plls[apll].rate_table = in exynos4_clk_init()
1282 exynos4x12_plls[apll].rate_table = in exynos4_clk_init()
Dclk-exynos5410.c61 apll, cpll, epll, mpll, enumerator
240 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
Dclk-s5pv210.c68 apll, enumerator
716 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
728 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
Dclk-exynos5420.c150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1462 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1486 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ argument
1487 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1598 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; in exynos5x_clk_init()
/linux-5.19.10/drivers/clk/ti/
DMakefile6 fixed-factor.o mux.o apll.o \
/linux-5.19.10/Documentation/devicetree/bindings/phy/
Dti-phy.txt48 * "phy-div" - divider for apll
49 * "div-clk" - apll clock
/linux-5.19.10/sound/soc/mediatek/mt8195/
Dmt8195-afe-clk.h101 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
Dmt8195-dai-etdm.c1843 int apll; in mtk_dai_etdm_mclk_configure() local
1863 apll = etdm_data->mclk_apll; in mtk_dai_etdm_mclk_configure()
1864 apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll); in mtk_dai_etdm_mclk_configure()
2065 int apll; in mtk_dai_etdm_cal_mclk() local
2073 apll = mt8195_afe_get_default_mclk_source_by_rate(freq); in mtk_dai_etdm_cal_mclk()
2074 apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll); in mtk_dai_etdm_cal_mclk()
2082 dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll); in mtk_dai_etdm_cal_mclk()
2086 etdm_data->mclk_apll = apll; in mtk_dai_etdm_cal_mclk()
Dmt8195-afe-clk.c358 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) in mt8195_afe_get_mclk_source_rate() argument
361 int clk_id = mt8195_afe_get_mclk_source_clk_id(apll); in mt8195_afe_get_mclk_source_rate()
/linux-5.19.10/drivers/clk/rockchip/
Dclk-rk3036.c21 apll, dpll, gpll, enumerator
137 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
Dclk-rk3188.c19 apll, cpll, dpll, gpll, enumerator
216 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
227 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
Dclk-rk3128.c18 apll, dpll, cpll, gpll, enumerator
159 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
Dclk-rk3228.c19 apll, dpll, cpll, gpll, enumerator
169 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
Dclk-rv1108.c19 apll, dpll, gpll, enumerator
154 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
/linux-5.19.10/drivers/ptp/
Dptp_clockmatrix.c351 u8 apll = 0; in wait_for_sys_apll_dpll_lock() local
356 err = read_sys_apll_status(idtcm, &apll); in wait_for_sys_apll_dpll_lock()
364 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK; in wait_for_sys_apll_dpll_lock()
367 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED && in wait_for_sys_apll_dpll_lock()
383 LOCK_TIMEOUT_MS, apll, dpll); in wait_for_sys_apll_dpll_lock()

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