Searched refs:__aligned (Results 1 – 25 of 627) sorted by relevance
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97 } __packed __aligned(8);110 } __packed __aligned(8);145 } __packed __aligned(8);163 } __packed __aligned(8);175 } __packed __aligned(8);184 } __packed __aligned(8);212 } __packed __aligned(8);240 } __packed __aligned(8);252 } __packed __aligned(8);288 } __packed __aligned(8);[all …]
147 } __packed __aligned(8);152 } __packed __aligned(8);156 } __packed __aligned(8);186 } __packed __aligned(8);195 } __packed __aligned(4);211 } __packed __aligned(4);239 } __packed __aligned(8);244 } __packed __aligned(8);251 } __packed __aligned(8);264 } __packed __aligned(8);[all …]
87 u32 num_output_formats __aligned(8);91 u32 num_vf_formats __aligned(8);97 u64 imgu_fw_blob_descr_ptr __aligned(8);98 u32 blob_index __aligned(8);99 union imgu_fw_all_memory_offsets mem_offsets __aligned(8);100 struct imgu_fw_binary_xinfo *next __aligned(8);152 u32 type __aligned(8); /* enum imgu_fw_type */159 u32 loaded __aligned(8); /* Firmware has been loaded */160 const u64 isp_code __aligned(8); /* ISP pointer to code */162 u32 handle __aligned(8);
727 operation_list[IMGU_ABI_SHD_MAX_OPERATIONS] __aligned(32);729 process_lines_data[IMGU_ABI_SHD_MAX_PROCESS_LINES] __aligned(32);731 transfer_data[IMGU_ABI_SHD_MAX_TRANSFERS] __aligned(32);735 struct ipu3_uapi_shd_config_static shd __aligned(32);736 struct imgu_abi_shd_intra_frame_operations_data shd_ops __aligned(32);737 struct ipu3_uapi_shd_lut shd_lut __aligned(32);850 struct imgu_abi_input_feeder_data data __aligned(32);861 __aligned(32);891 ops[IMGU_ABI_DVS_STAT_MAX_OPERATIONS] __aligned(32);894 __aligned(32);[all …]
62 __aligned(4);68 __aligned(4);70 __aligned(4);78 __aligned(4);82 __aligned(4);87 __aligned(4);91 __aligned(4);
56 } __aligned(16);67 } __aligned(16);77 } __aligned(16);99 } __aligned(64);111 } __aligned(16);127 } __aligned(32);140 } __aligned(32);150 } __aligned(16);159 } __aligned(8);169 } __aligned(16);
31 } __packed __aligned(4);47 } __packed __aligned(4);158 } __packed __aligned(4);218 } __packed __aligned(4);279 } __packed __aligned(4);319 } __packed __aligned(4);329 } __packed __aligned(4);339 } __packed __aligned(4);358 } __packed __aligned(4);
71 uint32_t ib[256] __aligned(256);75 } __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS];85 uint32_t ib[256] __aligned(256);89 } __aligned(PAGE_SIZE) compute[AMDGPU_MES_CTX_MAX_COMPUTE_RINGS];100 uint32_t ib[256] __aligned(256);104 } __aligned(PAGE_SIZE) sdma[AMDGPU_MES_CTX_MAX_SDMA_RINGS];
93 } __packed __aligned(8);114 } __packed __aligned(8);123 } __packed __aligned(8);138 } __packed __aligned(8);151 } __packed __aligned(8);159 } __packed __aligned(8);166 } __packed __aligned(8);177 } __packed __aligned(8);187 } __packed __aligned(8);214 } __packed __aligned(8);[all …]
38 } __packed __aligned(1);60 } __packed __aligned(1);88 } __packed __aligned(1);95 } __aligned(1);102 } __aligned(1);126 } __packed __aligned(1);133 } __aligned(1);
263 __le64 rbase __packed __aligned(4);264 __le64 rlen __packed __aligned(4);265 __le64 rp __packed __aligned(4);266 __le64 wp __packed __aligned(4);278 __le64 rbase __packed __aligned(4);279 __le64 rlen __packed __aligned(4);280 __le64 rp __packed __aligned(4);281 __le64 wp __packed __aligned(4);289 __le64 rbase __packed __aligned(4);290 __le64 rlen __packed __aligned(4);[all …]
12 } __aligned(1);29 } __aligned(1);39 } __aligned(1);55 } __aligned(1);
39 } __packed __aligned(CCB_ALIGN);93 } __packed __aligned(CSB_ALIGN);111 } __packed __aligned(DDE_ALIGN);123 } __packed __aligned(NX_STAMP_ALIGN);159 } __aligned(128);
112 } __packed __aligned(2);126 } __packed __aligned(2);133 } __packed __aligned(2);142 } __packed __aligned(2);151 } __packed __aligned(2);161 } __packed __aligned(2);
189 struct vnt_rx_desc *next __aligned(8);190 struct vnt_rd_info *rd_info __aligned(8);232 struct vnt_tx_desc *next __aligned(8);233 struct vnt_td_info *td_info __aligned(8);
38 } __packed __aligned(4);61 } __packed __aligned(4);84 } __packed __aligned(4);90 } __packed __aligned(4);
33 } __aligned(CCB_ALIGN);82 } __aligned(CSB_ALIGN);100 } __aligned(DDE_ALIGN);133 } __aligned(CRB_ALIGN);
77 } __aligned(16);101 } __aligned(16);133 } __aligned(16);150 } __aligned(16);287 } __aligned(128);321 } __aligned(128);326 } __aligned(2048);637 } __aligned(128);
28 } __packed __aligned(4) msg = { in mt76x2_mcu_set_channel()57 } __packed __aligned(4) msg = { in mt76x2_mcu_load_cr()81 } __packed __aligned(4) msg = { in mt76x2_mcu_init_gain()100 } __packed __aligned(4) msg = { in mt76x2_mcu_tssi_comp()
19 } __packed __aligned(4);27 } __packed __aligned(4);33 } __packed __aligned(4);38 } __packed __aligned(4);
281 } __packed __aligned(4);331 } __packed __aligned(4);370 struct ieee80211_hdr i3e __packed __aligned(2);377 struct ieee80211_hdr i3e __packed __aligned(2);382 struct ieee80211_hdr i3e __packed __aligned(2);387 struct ieee80211_hdr i3e __packed __aligned(2);
103 } __packed __aligned(4);109 } __packed __aligned(4);243 } __packed __aligned(4);244 } __packed __aligned(4);332 } __packed __aligned(4);
110 struct srp_direct_buf table_desc __packed __aligned(4);112 struct srp_direct_buf desc_list[] __packed __aligned(4);178 u64 tag __packed __aligned(4);261 u64 tag __packed __aligned(4);296 u64 tag __packed __aligned(4);
73 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_fork_connector()103 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_exec_connector()127 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_id_connector()165 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_sid_connector()189 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_ptrace_connector()221 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_comm_connector()247 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_coredump_connector()280 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in proc_exit_connector()322 __u8 buffer[CN_PROC_MSG_SIZE] __aligned(8); in cn_proc_ack()
287 s8 cpu __aligned(__CACHE_WRITEBACK_GRANULE);291 s8 cluster __aligned(__CACHE_WRITEBACK_GRANULE);294 s8 inbound __aligned(__CACHE_WRITEBACK_GRANULE);