1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _mipi_backend_defs_h 17 #define _mipi_backend_defs_h 18 19 #include "mipi_backend_common_defs.h" 20 21 #define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width 22 23 #define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut 24 25 // SH Backend Register IDs 26 #define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 27 #define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 28 //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 29 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 30 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 31 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 32 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 33 #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 34 #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 35 #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 36 #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 37 #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 38 //// 39 #define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 40 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 41 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 42 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 43 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 44 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 45 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 46 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 47 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 48 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 49 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 50 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 51 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 52 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 53 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 54 //// 55 #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 56 #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 57 //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 58 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 59 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 60 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 61 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 62 63 #define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries 64 65 #define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 66 67 ///////////////////////////////////////////////////////////////////////////////////////////////////// 68 #define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 69 #define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 70 //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 71 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 72 #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 73 #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 74 #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 75 #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS 76 #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 77 #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 78 #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1 + 2 + 6 79 //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 80 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 81 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 82 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 83 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 84 85 ///////////////////////////////////////////////////////////////////////////////////////////////////// 86 87 #define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 88 89 //#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration 90 91 #define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 92 #define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 93 #define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 94 95 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 96 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) 97 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) 98 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) 99 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) 100 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) 101 #define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) 102 #define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) 103 #define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) 104 105 /*************************************************************************************************/ 106 /* Custom Decoding */ 107 /* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ 108 /*************************************************************************************************/ 109 #define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ 110 #define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ 111 #define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit 112 #define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 113 #define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ 114 #define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ 115 116 #define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 117 118 /* Data State config = {get_bits(6bits), valid(1bit)} */ 119 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ 120 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ 121 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ 122 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ 123 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ 124 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ 125 126 /* Pixel Extractor config */ 127 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ 128 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ 129 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ 130 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ 131 132 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ 133 134 /* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ 135 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ 136 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ 137 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ 138 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ 139 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 140 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ 141 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ 142 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ 143 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ 144 145 /*************************************************************************************************/ 146 /* MIPI backend output streaming interface definition */ 147 /* These parameters define the fields within the streaming bus. These should also be used by the */ 148 /* subsequent block, ie stream2mmio. */ 149 /*************************************************************************************************/ 150 /* The pipe backend - stream2mmio should be design time configurable in */ 151 /* PixWidth - Number of bits per pixel */ 152 /* PPC - Pixel per Clocks */ 153 /* NumSids - Max number of source Ids (ifc's) and derived from that: */ 154 /* SidWidth - Number of bits required for the sid parameter */ 155 /* In order to keep this configurability, below Macro's have these as a parameter */ 156 /*************************************************************************************************/ 157 158 #define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 159 #define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 160 #define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 161 #define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 162 #define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 163 #define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT + (sid_width) - 1) 164 #define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) + 1 + p) 165 166 #define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, ppc) + ((pix_width) * p)) 167 #define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) + (pix_width) - 1) 168 169 #if 0 170 //#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 171 //#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 172 //#define HRT_MIPI_BACKEND_STREAM_PPC 4 173 #endif 174 175 #define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, (ppc - 1)) + 1) 176 177 /* SP and LP LUT BIT POSITIONS */ 178 #define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 179 #define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 180 #define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT + (sid_width) - 1) // 1 + (4) - 1 = 4 181 #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 182 #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 183 #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 184 #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 185 186 /* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ 187 188 #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 189 #define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 190 191 // temp solution 192 //#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 193 //#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 194 //#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 195 //#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 196 //#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 197 //#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 198 //#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 199 //#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 200 //#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 201 //#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 202 //#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 203 //#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 204 205 // vc hidden in pixb data (passed as raw12 the pipe) 206 #define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, 1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 207 #define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) + 1 // 37 208 209 #endif /* _mipi_backend_defs_h */ 210