1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2021 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
15
16 #include <linux/err.h>
17
18 #define ZYNQMP_PM_VERSION_MAJOR 1
19 #define ZYNQMP_PM_VERSION_MINOR 0
20
21 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24 #define ZYNQMP_TZ_VERSION_MAJOR 1
25 #define ZYNQMP_TZ_VERSION_MINOR 0
26
27 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30 /* SMC SIP service Call Function Identifier Prefix */
31 #define PM_SIP_SVC 0xC2000000
32
33 /* PM API versions */
34 #define PM_API_VERSION_2 2
35
36 /* ATF only commands */
37 #define PM_GET_TRUSTZONE_VERSION 0xa03
38 #define PM_SET_SUSPEND_MODE 0xa02
39 #define GET_CALLBACK_DATA 0xa01
40
41 /* Number of 32bits values in payload */
42 #define PAYLOAD_ARG_CNT 4U
43
44 /* Number of arguments for a callback */
45 #define CB_ARG_CNT 4
46
47 /* Payload size (consists of callback API ID + arguments) */
48 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
49
50 #define ZYNQMP_PM_MAX_QOS 100U
51
52 #define GSS_NUM_REGS (4)
53
54 /* Node capabilities */
55 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
56 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
57 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
58 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
59
60 /* Loader commands */
61 #define PM_LOAD_PDI 0x701
62 #define PDI_SRC_DDR 0xF
63
64 /*
65 * Firmware FPGA Manager flags
66 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
67 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
68 */
69 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
70 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
71
72 /*
73 * Node IDs for the Error Events.
74 */
75 #define EVENT_ERROR_PMC_ERR1 (0x28100000U)
76 #define EVENT_ERROR_PMC_ERR2 (0x28104000U)
77 #define EVENT_ERROR_PSM_ERR1 (0x28108000U)
78 #define EVENT_ERROR_PSM_ERR2 (0x2810C000U)
79
80 enum pm_api_cb_id {
81 PM_INIT_SUSPEND_CB = 30,
82 PM_ACKNOWLEDGE_CB = 31,
83 PM_NOTIFY_CB = 32,
84 };
85
86 enum pm_api_id {
87 PM_GET_API_VERSION = 1,
88 PM_REGISTER_NOTIFIER = 5,
89 PM_SYSTEM_SHUTDOWN = 12,
90 PM_REQUEST_NODE = 13,
91 PM_RELEASE_NODE = 14,
92 PM_SET_REQUIREMENT = 15,
93 PM_RESET_ASSERT = 17,
94 PM_RESET_GET_STATUS = 18,
95 PM_MMIO_WRITE = 19,
96 PM_MMIO_READ = 20,
97 PM_PM_INIT_FINALIZE = 21,
98 PM_FPGA_LOAD = 22,
99 PM_FPGA_GET_STATUS = 23,
100 PM_GET_CHIPID = 24,
101 PM_SECURE_SHA = 26,
102 PM_PINCTRL_REQUEST = 28,
103 PM_PINCTRL_RELEASE = 29,
104 PM_PINCTRL_GET_FUNCTION = 30,
105 PM_PINCTRL_SET_FUNCTION = 31,
106 PM_PINCTRL_CONFIG_PARAM_GET = 32,
107 PM_PINCTRL_CONFIG_PARAM_SET = 33,
108 PM_IOCTL = 34,
109 PM_QUERY_DATA = 35,
110 PM_CLOCK_ENABLE = 36,
111 PM_CLOCK_DISABLE = 37,
112 PM_CLOCK_GETSTATE = 38,
113 PM_CLOCK_SETDIVIDER = 39,
114 PM_CLOCK_GETDIVIDER = 40,
115 PM_CLOCK_SETRATE = 41,
116 PM_CLOCK_GETRATE = 42,
117 PM_CLOCK_SETPARENT = 43,
118 PM_CLOCK_GETPARENT = 44,
119 PM_SECURE_AES = 47,
120 PM_FEATURE_CHECK = 63,
121 };
122
123 /* PMU-FW return status codes */
124 enum pm_ret_status {
125 XST_PM_SUCCESS = 0,
126 XST_PM_NO_FEATURE = 19,
127 XST_PM_INTERNAL = 2000,
128 XST_PM_CONFLICT = 2001,
129 XST_PM_NO_ACCESS = 2002,
130 XST_PM_INVALID_NODE = 2003,
131 XST_PM_DOUBLE_REQ = 2004,
132 XST_PM_ABORT_SUSPEND = 2005,
133 XST_PM_MULT_USER = 2008,
134 };
135
136 enum pm_ioctl_id {
137 IOCTL_SD_DLL_RESET = 6,
138 IOCTL_SET_SD_TAPDELAY = 7,
139 IOCTL_SET_PLL_FRAC_MODE = 8,
140 IOCTL_GET_PLL_FRAC_MODE = 9,
141 IOCTL_SET_PLL_FRAC_DATA = 10,
142 IOCTL_GET_PLL_FRAC_DATA = 11,
143 IOCTL_WRITE_GGS = 12,
144 IOCTL_READ_GGS = 13,
145 IOCTL_WRITE_PGGS = 14,
146 IOCTL_READ_PGGS = 15,
147 /* Set healthy bit value */
148 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
149 IOCTL_OSPI_MUX_SELECT = 21,
150 /* Register SGI to ATF */
151 IOCTL_REGISTER_SGI = 25,
152 /* Runtime feature configuration */
153 IOCTL_SET_FEATURE_CONFIG = 26,
154 IOCTL_GET_FEATURE_CONFIG = 27,
155 };
156
157 enum pm_query_id {
158 PM_QID_INVALID = 0,
159 PM_QID_CLOCK_GET_NAME = 1,
160 PM_QID_CLOCK_GET_TOPOLOGY = 2,
161 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
162 PM_QID_CLOCK_GET_PARENTS = 4,
163 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
164 PM_QID_PINCTRL_GET_NUM_PINS = 6,
165 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
166 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
167 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
168 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
169 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
170 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
171 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
172 };
173
174 enum zynqmp_pm_reset_action {
175 PM_RESET_ACTION_RELEASE = 0,
176 PM_RESET_ACTION_ASSERT = 1,
177 PM_RESET_ACTION_PULSE = 2,
178 };
179
180 enum zynqmp_pm_reset {
181 ZYNQMP_PM_RESET_START = 1000,
182 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
183 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
184 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
185 ZYNQMP_PM_RESET_DP = 1003,
186 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
187 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
188 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
189 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
190 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
191 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
192 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
193 ZYNQMP_PM_RESET_GDMA = 1011,
194 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
195 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
196 ZYNQMP_PM_RESET_GPU = 1014,
197 ZYNQMP_PM_RESET_GT = 1015,
198 ZYNQMP_PM_RESET_SATA = 1016,
199 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
200 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
201 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
202 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
203 ZYNQMP_PM_RESET_APU_L2 = 1021,
204 ZYNQMP_PM_RESET_ACPU3 = 1022,
205 ZYNQMP_PM_RESET_ACPU2 = 1023,
206 ZYNQMP_PM_RESET_ACPU1 = 1024,
207 ZYNQMP_PM_RESET_ACPU0 = 1025,
208 ZYNQMP_PM_RESET_DDR = 1026,
209 ZYNQMP_PM_RESET_APM_FPD = 1027,
210 ZYNQMP_PM_RESET_SOFT = 1028,
211 ZYNQMP_PM_RESET_GEM0 = 1029,
212 ZYNQMP_PM_RESET_GEM1 = 1030,
213 ZYNQMP_PM_RESET_GEM2 = 1031,
214 ZYNQMP_PM_RESET_GEM3 = 1032,
215 ZYNQMP_PM_RESET_QSPI = 1033,
216 ZYNQMP_PM_RESET_UART0 = 1034,
217 ZYNQMP_PM_RESET_UART1 = 1035,
218 ZYNQMP_PM_RESET_SPI0 = 1036,
219 ZYNQMP_PM_RESET_SPI1 = 1037,
220 ZYNQMP_PM_RESET_SDIO0 = 1038,
221 ZYNQMP_PM_RESET_SDIO1 = 1039,
222 ZYNQMP_PM_RESET_CAN0 = 1040,
223 ZYNQMP_PM_RESET_CAN1 = 1041,
224 ZYNQMP_PM_RESET_I2C0 = 1042,
225 ZYNQMP_PM_RESET_I2C1 = 1043,
226 ZYNQMP_PM_RESET_TTC0 = 1044,
227 ZYNQMP_PM_RESET_TTC1 = 1045,
228 ZYNQMP_PM_RESET_TTC2 = 1046,
229 ZYNQMP_PM_RESET_TTC3 = 1047,
230 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
231 ZYNQMP_PM_RESET_NAND = 1049,
232 ZYNQMP_PM_RESET_ADMA = 1050,
233 ZYNQMP_PM_RESET_GPIO = 1051,
234 ZYNQMP_PM_RESET_IOU_CC = 1052,
235 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
236 ZYNQMP_PM_RESET_RPU_R50 = 1054,
237 ZYNQMP_PM_RESET_RPU_R51 = 1055,
238 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
239 ZYNQMP_PM_RESET_OCM = 1057,
240 ZYNQMP_PM_RESET_RPU_PGE = 1058,
241 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
242 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
243 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
244 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
245 ZYNQMP_PM_RESET_USB0_APB = 1063,
246 ZYNQMP_PM_RESET_USB1_APB = 1064,
247 ZYNQMP_PM_RESET_IPI = 1065,
248 ZYNQMP_PM_RESET_APM_LPD = 1066,
249 ZYNQMP_PM_RESET_RTC = 1067,
250 ZYNQMP_PM_RESET_SYSMON = 1068,
251 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
252 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
253 ZYNQMP_PM_RESET_FPD = 1071,
254 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
255 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
256 ZYNQMP_PM_RESET_DBG_LPD = 1074,
257 ZYNQMP_PM_RESET_DBG_FPD = 1075,
258 ZYNQMP_PM_RESET_APLL = 1076,
259 ZYNQMP_PM_RESET_DPLL = 1077,
260 ZYNQMP_PM_RESET_VPLL = 1078,
261 ZYNQMP_PM_RESET_IOPLL = 1079,
262 ZYNQMP_PM_RESET_RPLL = 1080,
263 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
264 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
265 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
266 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
267 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
268 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
269 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
270 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
271 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
272 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
273 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
274 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
275 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
276 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
277 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
278 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
279 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
280 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
281 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
282 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
283 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
284 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
285 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
286 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
287 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
288 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
289 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
290 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
291 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
292 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
293 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
294 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
295 ZYNQMP_PM_RESET_RPU_LS = 1113,
296 ZYNQMP_PM_RESET_PS_ONLY = 1114,
297 ZYNQMP_PM_RESET_PL = 1115,
298 ZYNQMP_PM_RESET_PS_PL0 = 1116,
299 ZYNQMP_PM_RESET_PS_PL1 = 1117,
300 ZYNQMP_PM_RESET_PS_PL2 = 1118,
301 ZYNQMP_PM_RESET_PS_PL3 = 1119,
302 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
303 };
304
305 enum zynqmp_pm_suspend_reason {
306 SUSPEND_POWER_REQUEST = 201,
307 SUSPEND_ALERT = 202,
308 SUSPEND_SYSTEM_SHUTDOWN = 203,
309 };
310
311 enum zynqmp_pm_request_ack {
312 ZYNQMP_PM_REQUEST_ACK_NO = 1,
313 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
314 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
315 };
316
317 enum pm_node_id {
318 NODE_SD_0 = 39,
319 NODE_SD_1 = 40,
320 };
321
322 enum tap_delay_type {
323 PM_TAPDELAY_INPUT = 0,
324 PM_TAPDELAY_OUTPUT = 1,
325 };
326
327 enum dll_reset_type {
328 PM_DLL_RESET_ASSERT = 0,
329 PM_DLL_RESET_RELEASE = 1,
330 PM_DLL_RESET_PULSE = 2,
331 };
332
333 enum pm_pinctrl_config_param {
334 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
335 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
336 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
337 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
338 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
339 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
340 PM_PINCTRL_CONFIG_TRI_STATE = 6,
341 PM_PINCTRL_CONFIG_MAX = 7,
342 };
343
344 enum pm_pinctrl_slew_rate {
345 PM_PINCTRL_SLEW_RATE_FAST = 0,
346 PM_PINCTRL_SLEW_RATE_SLOW = 1,
347 };
348
349 enum pm_pinctrl_bias_status {
350 PM_PINCTRL_BIAS_DISABLE = 0,
351 PM_PINCTRL_BIAS_ENABLE = 1,
352 };
353
354 enum pm_pinctrl_pull_ctrl {
355 PM_PINCTRL_BIAS_PULL_DOWN = 0,
356 PM_PINCTRL_BIAS_PULL_UP = 1,
357 };
358
359 enum pm_pinctrl_schmitt_cmos {
360 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
361 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
362 };
363
364 enum pm_pinctrl_drive_strength {
365 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
366 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
367 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
368 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
369 };
370
371 enum zynqmp_pm_shutdown_type {
372 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
373 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
374 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
375 };
376
377 enum zynqmp_pm_shutdown_subtype {
378 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
379 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
380 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
381 };
382
383 enum ospi_mux_select_type {
384 PM_OSPI_MUX_SEL_DMA = 0,
385 PM_OSPI_MUX_SEL_LINEAR = 1,
386 };
387
388 enum pm_feature_config_id {
389 PM_FEATURE_INVALID = 0,
390 PM_FEATURE_OVERTEMP_STATUS = 1,
391 PM_FEATURE_OVERTEMP_VALUE = 2,
392 PM_FEATURE_EXTWDT_STATUS = 3,
393 PM_FEATURE_EXTWDT_VALUE = 4,
394 };
395
396 /**
397 * struct zynqmp_pm_query_data - PM query data
398 * @qid: query ID
399 * @arg1: Argument 1 of query data
400 * @arg2: Argument 2 of query data
401 * @arg3: Argument 3 of query data
402 */
403 struct zynqmp_pm_query_data {
404 u32 qid;
405 u32 arg1;
406 u32 arg2;
407 u32 arg3;
408 };
409
410 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
411 u32 arg2, u32 arg3, u32 *ret_payload);
412
413 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
414 int zynqmp_pm_get_api_version(u32 *version);
415 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
416 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
417 int zynqmp_pm_clock_enable(u32 clock_id);
418 int zynqmp_pm_clock_disable(u32 clock_id);
419 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
420 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
421 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
422 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
423 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
424 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
425 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
426 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
427 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
428 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
429 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
430 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
431 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
432 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
433 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
434 const enum zynqmp_pm_reset_action assert_flag);
435 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
436 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
437 int zynqmp_pm_bootmode_write(u32 ps_mode);
438 int zynqmp_pm_init_finalize(void);
439 int zynqmp_pm_set_suspend_mode(u32 mode);
440 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
441 const u32 qos, const enum zynqmp_pm_request_ack ack);
442 int zynqmp_pm_release_node(const u32 node);
443 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
444 const u32 qos,
445 const enum zynqmp_pm_request_ack ack);
446 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
447 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
448 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
449 int zynqmp_pm_fpga_get_status(u32 *value);
450 int zynqmp_pm_write_ggs(u32 index, u32 value);
451 int zynqmp_pm_read_ggs(u32 index, u32 *value);
452 int zynqmp_pm_write_pggs(u32 index, u32 value);
453 int zynqmp_pm_read_pggs(u32 index, u32 *value);
454 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
455 int zynqmp_pm_set_boot_health_status(u32 value);
456 int zynqmp_pm_pinctrl_request(const u32 pin);
457 int zynqmp_pm_pinctrl_release(const u32 pin);
458 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
459 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
460 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
461 u32 *value);
462 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
463 u32 value);
464 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
465 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
466 const u32 wake, const u32 enable);
467 int zynqmp_pm_feature(const u32 api_id);
468 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
469 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
470 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
471 #else
zynqmp_pm_get_api_version(u32 * version)472 static inline int zynqmp_pm_get_api_version(u32 *version)
473 {
474 return -ENODEV;
475 }
476
zynqmp_pm_get_chipid(u32 * idcode,u32 * version)477 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
478 {
479 return -ENODEV;
480 }
481
zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)482 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
483 u32 *out)
484 {
485 return -ENODEV;
486 }
487
zynqmp_pm_clock_enable(u32 clock_id)488 static inline int zynqmp_pm_clock_enable(u32 clock_id)
489 {
490 return -ENODEV;
491 }
492
zynqmp_pm_clock_disable(u32 clock_id)493 static inline int zynqmp_pm_clock_disable(u32 clock_id)
494 {
495 return -ENODEV;
496 }
497
zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)498 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
499 {
500 return -ENODEV;
501 }
502
zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)503 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
504 {
505 return -ENODEV;
506 }
507
zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)508 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
509 {
510 return -ENODEV;
511 }
512
zynqmp_pm_clock_setrate(u32 clock_id,u64 rate)513 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
514 {
515 return -ENODEV;
516 }
517
zynqmp_pm_clock_getrate(u32 clock_id,u64 * rate)518 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
519 {
520 return -ENODEV;
521 }
522
zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)523 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
524 {
525 return -ENODEV;
526 }
527
zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)528 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
529 {
530 return -ENODEV;
531 }
532
zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)533 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
534 {
535 return -ENODEV;
536 }
537
zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)538 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
539 {
540 return -ENODEV;
541 }
542
zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)543 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
544 {
545 return -ENODEV;
546 }
547
zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)548 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
549 {
550 return -ENODEV;
551 }
552
zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)553 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
554 {
555 return -ENODEV;
556 }
557
zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)558 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
559 {
560 return -ENODEV;
561 }
562
zynqmp_pm_ospi_mux_select(u32 dev_id,u32 select)563 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
564 {
565 return -ENODEV;
566 }
567
zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,const enum zynqmp_pm_reset_action assert_flag)568 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
569 const enum zynqmp_pm_reset_action assert_flag)
570 {
571 return -ENODEV;
572 }
573
zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,u32 * status)574 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
575 u32 *status)
576 {
577 return -ENODEV;
578 }
579
zynqmp_pm_bootmode_read(u32 * ps_mode)580 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
581 {
582 return -ENODEV;
583 }
584
zynqmp_pm_bootmode_write(u32 ps_mode)585 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
586 {
587 return -ENODEV;
588 }
589
zynqmp_pm_init_finalize(void)590 static inline int zynqmp_pm_init_finalize(void)
591 {
592 return -ENODEV;
593 }
594
zynqmp_pm_set_suspend_mode(u32 mode)595 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
596 {
597 return -ENODEV;
598 }
599
zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)600 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
601 const u32 qos,
602 const enum zynqmp_pm_request_ack ack)
603 {
604 return -ENODEV;
605 }
606
zynqmp_pm_release_node(const u32 node)607 static inline int zynqmp_pm_release_node(const u32 node)
608 {
609 return -ENODEV;
610 }
611
zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)612 static inline int zynqmp_pm_set_requirement(const u32 node,
613 const u32 capabilities,
614 const u32 qos,
615 const enum zynqmp_pm_request_ack ack)
616 {
617 return -ENODEV;
618 }
619
zynqmp_pm_aes_engine(const u64 address,u32 * out)620 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
621 {
622 return -ENODEV;
623 }
624
zynqmp_pm_sha_hash(const u64 address,const u32 size,const u32 flags)625 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
626 const u32 flags)
627 {
628 return -ENODEV;
629 }
630
zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)631 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
632 const u32 flags)
633 {
634 return -ENODEV;
635 }
636
zynqmp_pm_fpga_get_status(u32 * value)637 static inline int zynqmp_pm_fpga_get_status(u32 *value)
638 {
639 return -ENODEV;
640 }
641
zynqmp_pm_write_ggs(u32 index,u32 value)642 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
643 {
644 return -ENODEV;
645 }
646
zynqmp_pm_read_ggs(u32 index,u32 * value)647 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
648 {
649 return -ENODEV;
650 }
651
zynqmp_pm_write_pggs(u32 index,u32 value)652 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
653 {
654 return -ENODEV;
655 }
656
zynqmp_pm_read_pggs(u32 index,u32 * value)657 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
658 {
659 return -ENODEV;
660 }
661
zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)662 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
663 {
664 return -ENODEV;
665 }
666
zynqmp_pm_set_boot_health_status(u32 value)667 static inline int zynqmp_pm_set_boot_health_status(u32 value)
668 {
669 return -ENODEV;
670 }
671
zynqmp_pm_pinctrl_request(const u32 pin)672 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
673 {
674 return -ENODEV;
675 }
676
zynqmp_pm_pinctrl_release(const u32 pin)677 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
678 {
679 return -ENODEV;
680 }
681
zynqmp_pm_pinctrl_get_function(const u32 pin,u32 * id)682 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
683 {
684 return -ENODEV;
685 }
686
zynqmp_pm_is_function_supported(const u32 api_id,const u32 id)687 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
688 {
689 return -ENODEV;
690 }
691
zynqmp_pm_pinctrl_set_function(const u32 pin,const u32 id)692 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
693 {
694 return -ENODEV;
695 }
696
zynqmp_pm_pinctrl_get_config(const u32 pin,const u32 param,u32 * value)697 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
698 u32 *value)
699 {
700 return -ENODEV;
701 }
702
zynqmp_pm_pinctrl_set_config(const u32 pin,const u32 param,u32 value)703 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
704 u32 value)
705 {
706 return -ENODEV;
707 }
708
zynqmp_pm_load_pdi(const u32 src,const u64 address)709 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
710 {
711 return -ENODEV;
712 }
713
zynqmp_pm_register_notifier(const u32 node,const u32 event,const u32 wake,const u32 enable)714 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
715 const u32 wake, const u32 enable)
716 {
717 return -ENODEV;
718 }
719
zynqmp_pm_feature(const u32 api_id)720 static inline int zynqmp_pm_feature(const u32 api_id)
721 {
722 return -ENODEV;
723 }
724
zynqmp_pm_set_feature_config(enum pm_feature_config_id id,u32 value)725 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
726 u32 value)
727 {
728 return -ENODEV;
729 }
730
zynqmp_pm_get_feature_config(enum pm_feature_config_id id,u32 * payload)731 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
732 u32 *payload)
733 {
734 return -ENODEV;
735 }
736 #endif
737
738 #endif /* __FIRMWARE_ZYNQMP_H__ */
739