| /linux-5.19.10/drivers/gpu/drm/radeon/ |
| D | trinity_smc.c | 66 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
68 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
75 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
82 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
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| D | trinity_dpm.c | 339 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
463 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
481 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
486 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
490 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
494 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
555 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
565 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
577 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
589 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()
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| D | ci_smc.c | 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
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| D | si_smc.c | 119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
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| D | ci_dpm.c | 575 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
865 WREG32_SMC(CG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
872 WREG32_SMC(CG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
889 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
898 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
925 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
929 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1103 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
1180 WREG32_SMC(CG_TACH_CTRL, tmp);
1196 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
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| D | kv_dpm.c | 191 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
368 WREG32_SMC(CG_FTV_0, 0x3FFFC100); in kv_program_vc()
373 WREG32_SMC(CG_FTV_0, 0); in kv_clear_vc()
491 WREG32_SMC(GENERAL_PWRMGT, tmp); in kv_start_dpm()
508 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_start_am()
517 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_reset_am()
1024 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int); in kv_enable_thermal_int()
2245 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1); in kv_program_nbps_index_settings()
2269 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp); in kv_set_thermal_temperature_range()
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| D | cik.c | 9422 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9469 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
9768 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
9774 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
9779 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
9784 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
9790 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
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| D | si.c | 5461 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5462 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5473 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5474 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
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| D | radeon.h | 2560 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2594 WREG32_SMC(reg, tmp_); \
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| D | si_dpm.c | 2744 WREG32_SMC(offset, data); in si_program_cac_config_registers()
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| /linux-5.19.10/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| D | si_smc.c | 117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc()
131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc()
150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_si_smc_clock()
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| D | kv_dpm.c | 404 WREG32_SMC(local_cac_reg->cntl, data);
444 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
535 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
536 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
539 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
540 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
543 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
544 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
547 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
548 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
[all …]
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| D | si_dpm.c | 2860 WREG32_SMC(offset, data); in si_program_cac_config_registers()
7562 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7567 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7579 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7584 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | cik.c | 997 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
1008 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1468 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1517 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1828 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1836 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1841 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1846 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1852 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
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| D | vi.c | 622 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
633 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
1004 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
1094 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
1224 WREG32_SMC(ixTHM_CLK_CNTL, data); in vi_program_aspm()
1233 WREG32_SMC(ixMISC_CLK_CTRL, data); in vi_program_aspm()
1238 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm()
1243 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in vi_program_aspm()
1249 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in vi_program_aspm()
1882 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
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| D | amdgpu_cgs.c | 94 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
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| D | amdgpu.h | 1143 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro
1176 WREG32_SMC(_Reg, tmp); \
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| D | vce_v4_0.c | 915 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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| D | amdgpu_debugfs.c | 689 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
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| D | uvd_v7_0.c | 1717 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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| D | gfx_v8_0.c | 802 WREG32_SMC(ixCG_ACLK_CNTL, data); in gfx_v8_0_init_golden_registers()
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