/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
D | dcn316_clk_mgr.c | 402 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn316_build_watermark_ranges() 403 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn316_build_watermark_ranges() 404 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges() 405 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn316_build_watermark_ranges() 406 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in dcn316_build_watermark_ranges()
|
D | dcn316_smu.h | 55 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
D | dcn30_smu11_driver_if.h | 38 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
D | vg_clk_mgr.c | 433 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in vg_build_watermark_ranges() 434 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in vg_build_watermark_ranges() 435 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in vg_build_watermark_ranges() 436 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in vg_build_watermark_ranges() 437 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in vg_build_watermark_ranges()
|
D | dcn301_smu.h | 70 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
D | dcn31_clk_mgr.c | 461 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn31_build_watermark_ranges() 462 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges() 463 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges() 464 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn31_build_watermark_ranges() 465 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in dcn31_build_watermark_ranges()
|
D | dcn31_smu.h | 67 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/ |
D | smu10_driver_if.h | 64 WM_SOCCLK = 0, enumerator
|
D | smu9_driver_if.h | 340 WM_SOCCLK = 0, enumerator
|
D | smu11_driver_if.h | 691 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
D | dcn315_clk_mgr.c | 396 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn315_build_watermark_ranges() 397 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn315_build_watermark_ranges() 398 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges() 399 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; in dcn315_build_watermark_ranges() 400 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; in dcn315_build_watermark_ranges()
|
D | dcn315_smu.h | 56 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
D | smu_v13_0_5_ppt.c | 417 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table() 419 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table() 421 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table() 423 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table() 426 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
|
D | smu_v13_0_4_ppt.c | 669 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table() 671 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table() 673 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table() 675 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table() 678 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
|
D | yellow_carp_ppt.c | 507 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table() 509 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table() 511 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in yellow_carp_set_watermarks_table() 513 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in yellow_carp_set_watermarks_table() 516 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
D | smu13_driver_if_v13_0_5.h | 66 WM_SOCCLK = 0, enumerator
|
D | smu13_driver_if_yellow_carp.h | 65 WM_SOCCLK = 0, enumerator
|
D | smu12_driver_if.h | 66 WM_SOCCLK = 0, enumerator
|
D | smu13_driver_if_v13_0_4.h | 66 WM_SOCCLK = 0, enumerator
|
D | smu11_driver_if_vangogh.h | 65 WM_SOCCLK = 0, enumerator
|
D | smu11_driver_if_navi10.h | 1035 WM_SOCCLK = 0, enumerator
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
D | renoir_ppt.c | 1063 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table() 1065 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table() 1067 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in renoir_set_watermarks_table() 1069 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in renoir_set_watermarks_table() 1072 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in renoir_set_watermarks_table() 1074 table->WatermarkRow[WM_SOCCLK][i].WmType = in renoir_set_watermarks_table()
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
D | vangogh_ppt.c | 1606 table->WatermarkRow[WM_SOCCLK][i].MinClock = in vangogh_set_watermarks_table() 1608 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in vangogh_set_watermarks_table() 1610 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in vangogh_set_watermarks_table() 1612 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in vangogh_set_watermarks_table() 1615 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in vangogh_set_watermarks_table()
|
D | navi10_ppt.c | 2140 table->WatermarkRow[WM_SOCCLK][i].MinClock = in navi10_set_watermarks_table() 2142 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in navi10_set_watermarks_table() 2144 table->WatermarkRow[WM_SOCCLK][i].MinUclk = in navi10_set_watermarks_table() 2146 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = in navi10_set_watermarks_table() 2149 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in navi10_set_watermarks_table()
|
/linux-5.19.10/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
D | smu9_driver_if.h | 584 WM_SOCCLK = 0, enumerator
|