1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * This file is part of wl12xx
4  *
5  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
6  * Copyright (C) 2009 Nokia Corporation
7  *
8  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
9  */
10 
11 #ifndef __REG_H__
12 #define __REG_H__
13 
14 #include <linux/bitops.h>
15 
16 #define REGISTERS_BASE 0x00300000
17 #define DRPW_BASE      0x00310000
18 
19 #define REGISTERS_DOWN_SIZE 0x00008800
20 #define REGISTERS_WORK_SIZE 0x0000b000
21 
22 #define FW_STATUS_ADDR                      (0x14FC0 + 0xA000)
23 
24 /*===============================================
25    Host Software Reset - 32bit RW
26  ------------------------------------------
27     [31:1] Reserved
28     0  SOFT_RESET Soft Reset  - When this bit is set,
29     it holds the Wlan hardware in a soft reset state.
30     This reset disables all MAC and baseband processor
31     clocks except the CardBus/PCI interface clock.
32     It also initializes all MAC state machines except
33     the host interface. It does not reload the
34     contents of the EEPROM. When this bit is cleared
35     (not self-clearing), the Wlan hardware
36     exits the software reset state.
37 ===============================================*/
38 #define WL12XX_SLV_SOFT_RESET		(REGISTERS_BASE + 0x0000)
39 
40 #define WL1271_SLV_REG_DATA            (REGISTERS_BASE + 0x0008)
41 #define WL1271_SLV_REG_ADATA           (REGISTERS_BASE + 0x000c)
42 #define WL1271_SLV_MEM_DATA            (REGISTERS_BASE + 0x0018)
43 
44 #define WL12XX_REG_INTERRUPT_TRIG         (REGISTERS_BASE + 0x0474)
45 #define WL12XX_REG_INTERRUPT_TRIG_H       (REGISTERS_BASE + 0x0478)
46 
47 /*=============================================
48   Host Interrupt Mask Register - 32bit (RW)
49   ------------------------------------------
50   Setting a bit in this register masks the
51   corresponding interrupt to the host.
52   0 - RX0		- Rx first dubble buffer Data Interrupt
53   1 - TXD		- Tx Data Interrupt
54   2 - TXXFR		- Tx Transfer Interrupt
55   3 - RX1		- Rx second dubble buffer Data Interrupt
56   4 - RXXFR		- Rx Transfer Interrupt
57   5 - EVENT_A	- Event Mailbox interrupt
58   6 - EVENT_B	- Event Mailbox interrupt
59   7 - WNONHST	- Wake On Host Interrupt
60   8 - TRACE_A	- Debug Trace interrupt
61   9 - TRACE_B	- Debug Trace interrupt
62  10 - CDCMP		- Command Complete Interrupt
63  11 -
64  12 -
65  13 -
66  14 - ICOMP		- Initialization Complete Interrupt
67  16 - SG SE		- Soft Gemini - Sense enable interrupt
68  17 - SG SD		- Soft Gemini - Sense disable interrupt
69  18 -			-
70  19 -			-
71  20 -			-
72  21-			-
73  Default: 0x0001
74 *==============================================*/
75 #define WL12XX_REG_INTERRUPT_MASK         (REGISTERS_BASE + 0x04DC)
76 
77 /*=============================================
78   Host Interrupt Mask Set 16bit, (Write only)
79   ------------------------------------------
80  Setting a bit in this register sets
81  the corresponding bin in ACX_HINT_MASK register
82  without effecting the mask
83  state of other bits (0 = no effect).
84 ==============================================*/
85 #define ACX_REG_HINT_MASK_SET          (REGISTERS_BASE + 0x04E0)
86 
87 /*=============================================
88   Host Interrupt Mask Clear 16bit,(Write only)
89   ------------------------------------------
90  Setting a bit in this register clears
91  the corresponding bin in ACX_HINT_MASK register
92  without effecting the mask
93  state of other bits (0 = no effect).
94 =============================================*/
95 #define ACX_REG_HINT_MASK_CLR          (REGISTERS_BASE + 0x04E4)
96 
97 /*=============================================
98   Host Interrupt Status Nondestructive Read
99   16bit,(Read only)
100   ------------------------------------------
101  The host can read this register to determine
102  which interrupts are active.
103  Reading this register doesn't
104  effect its content.
105 =============================================*/
106 #define WL12XX_REG_INTERRUPT_NO_CLEAR     (REGISTERS_BASE + 0x04E8)
107 
108 /*=============================================
109   Host Interrupt Status Clear on Read  Register
110   16bit,(Read only)
111   ------------------------------------------
112  The host can read this register to determine
113  which interrupts are active.
114  Reading this register clears it,
115  thus making all interrupts inactive.
116 ==============================================*/
117 #define ACX_REG_INTERRUPT_CLEAR        (REGISTERS_BASE + 0x04F8)
118 
119 /*=============================================
120   Host Interrupt Acknowledge Register
121   16bit,(Write only)
122   ------------------------------------------
123  The host can set individual bits in this
124  register to clear (acknowledge) the corresp.
125  interrupt status bits in the HINT_STS_CLR and
126  HINT_STS_ND registers, thus making the
127  assotiated interrupt inactive. (0-no effect)
128 ==============================================*/
129 #define WL12XX_REG_INTERRUPT_ACK          (REGISTERS_BASE + 0x04F0)
130 
131 #define WL12XX_REG_RX_DRIVER_COUNTER	(REGISTERS_BASE + 0x0538)
132 
133 /* Device Configuration registers*/
134 #define SOR_CFG                        (REGISTERS_BASE + 0x0800)
135 
136 /* Embedded ARM CPU Control */
137 
138 /*===============================================
139  Halt eCPU   - 32bit RW
140  ------------------------------------------
141  0 HALT_ECPU Halt Embedded CPU - This bit is the
142  complement of bit 1 (MDATA2) in the SOR_CFG register.
143  During a hardware reset, this bit holds
144  the inverse of MDATA2.
145  When downloading firmware from the host,
146  set this bit (pull down MDATA2).
147  The host clears this bit after downloading the firmware into
148  zero-wait-state SSRAM.
149  When loading firmware from Flash, clear this bit (pull up MDATA2)
150  so that the eCPU can run the bootloader code in Flash
151  HALT_ECPU eCPU State
152  --------------------
153  1 halt eCPU
154  0 enable eCPU
155  ===============================================*/
156 #define WL12XX_REG_ECPU_CONTROL           (REGISTERS_BASE + 0x0804)
157 
158 #define WL12XX_HI_CFG			(REGISTERS_BASE + 0x0808)
159 
160 /*===============================================
161  EEPROM Burst Read Start  - 32bit RW
162  ------------------------------------------
163  [31:1] Reserved
164  0  ACX_EE_START -  EEPROM Burst Read Start 0
165  Setting this bit starts a burst read from
166  the external EEPROM.
167  If this bit is set (after reset) before an EEPROM read/write,
168  the burst read starts at EEPROM address 0.
169  Otherwise, it starts at the address
170  following the address of the previous access.
171  TheWlan hardware hardware clears this bit automatically.
172 
173  Default: 0x00000000
174 *================================================*/
175 #define ACX_REG_EE_START               (REGISTERS_BASE + 0x080C)
176 
177 #define WL12XX_OCP_POR_CTR		(REGISTERS_BASE + 0x09B4)
178 #define WL12XX_OCP_DATA_WRITE		(REGISTERS_BASE + 0x09B8)
179 #define WL12XX_OCP_DATA_READ		(REGISTERS_BASE + 0x09BC)
180 #define WL12XX_OCP_CMD			(REGISTERS_BASE + 0x09C0)
181 
182 #define WL12XX_HOST_WR_ACCESS		(REGISTERS_BASE + 0x09F8)
183 
184 #define WL12XX_CHIP_ID_B		(REGISTERS_BASE + 0x5674)
185 
186 #define WL12XX_ENABLE			(REGISTERS_BASE + 0x5450)
187 
188 /* Power Management registers */
189 #define WL12XX_ELP_CFG_MODE		(REGISTERS_BASE + 0x5804)
190 #define WL12XX_ELP_CMD			(REGISTERS_BASE + 0x5808)
191 #define WL12XX_PLL_CAL_TIME		(REGISTERS_BASE + 0x5810)
192 #define WL12XX_CLK_REQ_TIME		(REGISTERS_BASE + 0x5814)
193 #define WL12XX_CLK_BUF_TIME		(REGISTERS_BASE + 0x5818)
194 
195 #define WL12XX_CFG_PLL_SYNC_CNT		(REGISTERS_BASE + 0x5820)
196 
197 /* Scratch Pad registers*/
198 #define WL12XX_SCR_PAD0			(REGISTERS_BASE + 0x5608)
199 #define WL12XX_SCR_PAD1			(REGISTERS_BASE + 0x560C)
200 #define WL12XX_SCR_PAD2			(REGISTERS_BASE + 0x5610)
201 #define WL12XX_SCR_PAD3			(REGISTERS_BASE + 0x5614)
202 #define WL12XX_SCR_PAD4			(REGISTERS_BASE + 0x5618)
203 #define WL12XX_SCR_PAD4_SET		(REGISTERS_BASE + 0x561C)
204 #define WL12XX_SCR_PAD4_CLR		(REGISTERS_BASE + 0x5620)
205 #define WL12XX_SCR_PAD5			(REGISTERS_BASE + 0x5624)
206 #define WL12XX_SCR_PAD5_SET		(REGISTERS_BASE + 0x5628)
207 #define WL12XX_SCR_PAD5_CLR		(REGISTERS_BASE + 0x562C)
208 #define WL12XX_SCR_PAD6			(REGISTERS_BASE + 0x5630)
209 #define WL12XX_SCR_PAD7			(REGISTERS_BASE + 0x5634)
210 #define WL12XX_SCR_PAD8			(REGISTERS_BASE + 0x5638)
211 #define WL12XX_SCR_PAD9			(REGISTERS_BASE + 0x563C)
212 
213 /* Spare registers*/
214 #define WL12XX_SPARE_A1			(REGISTERS_BASE + 0x0994)
215 #define WL12XX_SPARE_A2			(REGISTERS_BASE + 0x0998)
216 #define WL12XX_SPARE_A3			(REGISTERS_BASE + 0x099C)
217 #define WL12XX_SPARE_A4			(REGISTERS_BASE + 0x09A0)
218 #define WL12XX_SPARE_A5			(REGISTERS_BASE + 0x09A4)
219 #define WL12XX_SPARE_A6			(REGISTERS_BASE + 0x09A8)
220 #define WL12XX_SPARE_A7			(REGISTERS_BASE + 0x09AC)
221 #define WL12XX_SPARE_A8			(REGISTERS_BASE + 0x09B0)
222 #define WL12XX_SPARE_B1			(REGISTERS_BASE + 0x5420)
223 #define WL12XX_SPARE_B2			(REGISTERS_BASE + 0x5424)
224 #define WL12XX_SPARE_B3			(REGISTERS_BASE + 0x5428)
225 #define WL12XX_SPARE_B4			(REGISTERS_BASE + 0x542C)
226 #define WL12XX_SPARE_B5			(REGISTERS_BASE + 0x5430)
227 #define WL12XX_SPARE_B6			(REGISTERS_BASE + 0x5434)
228 #define WL12XX_SPARE_B7			(REGISTERS_BASE + 0x5438)
229 #define WL12XX_SPARE_B8			(REGISTERS_BASE + 0x543C)
230 
231 #define WL12XX_PLL_PARAMETERS		(REGISTERS_BASE + 0x6040)
232 #define WL12XX_WU_COUNTER_PAUSE		(REGISTERS_BASE + 0x6008)
233 #define WL12XX_WELP_ARM_COMMAND		(REGISTERS_BASE + 0x6100)
234 #define WL12XX_DRPW_SCRATCH_START	(DRPW_BASE + 0x002C)
235 
236 #define WL12XX_CMD_MBOX_ADDRESS		0x407B4
237 
238 #define ACX_REG_EEPROM_START_BIT BIT(1)
239 
240 /* Command/Information Mailbox Pointers */
241 
242 /*===============================================
243   Command Mailbox Pointer - 32bit RW
244  ------------------------------------------
245  This register holds the start address of
246  the command mailbox located in the Wlan hardware memory.
247  The host must read this pointer after a reset to
248  find the location of the command mailbox.
249  The Wlan hardware initializes the command mailbox
250  pointer with the default address of the command mailbox.
251  The command mailbox pointer is not valid until after
252  the host receives the Init Complete interrupt from
253  the Wlan hardware.
254  ===============================================*/
255 #define WL12XX_REG_COMMAND_MAILBOX_PTR		(WL12XX_SCR_PAD0)
256 
257 /*===============================================
258   Information Mailbox Pointer - 32bit RW
259  ------------------------------------------
260  This register holds the start address of
261  the information mailbox located in the Wlan hardware memory.
262  The host must read this pointer after a reset to find
263  the location of the information mailbox.
264  The Wlan hardware initializes the information mailbox pointer
265  with the default address of the information mailbox.
266  The information mailbox pointer is not valid
267  until after the host receives the Init Complete interrupt from
268  the Wlan hardware.
269  ===============================================*/
270 #define WL12XX_REG_EVENT_MAILBOX_PTR		(WL12XX_SCR_PAD1)
271 
272 /*===============================================
273  EEPROM Read/Write Request 32bit RW
274  ------------------------------------------
275  1 EE_READ - EEPROM Read Request 1 - Setting this bit
276  loads a single byte of data into the EE_DATA
277  register from the EEPROM location specified in
278  the EE_ADDR register.
279  The Wlan hardware hardware clears this bit automatically.
280  EE_DATA is valid when this bit is cleared.
281 
282  0 EE_WRITE  - EEPROM Write Request  - Setting this bit
283  writes a single byte of data from the EE_DATA register into the
284  EEPROM location specified in the EE_ADDR register.
285  The Wlan hardware hardware clears this bit automatically.
286 *===============================================*/
287 #define ACX_EE_CTL_REG                      EE_CTL
288 #define EE_WRITE                            0x00000001ul
289 #define EE_READ                             0x00000002ul
290 
291 /*===============================================
292   EEPROM Address  - 32bit RW
293   ------------------------------------------
294   This register specifies the address
295   within the EEPROM from/to which to read/write data.
296   ===============================================*/
297 #define ACX_EE_ADDR_REG                     EE_ADDR
298 
299 /*===============================================
300   EEPROM Data  - 32bit RW
301   ------------------------------------------
302   This register either holds the read 8 bits of
303   data from the EEPROM or the write data
304   to be written to the EEPROM.
305   ===============================================*/
306 #define ACX_EE_DATA_REG                     EE_DATA
307 
308 /*===============================================
309   EEPROM Base Address  - 32bit RW
310   ------------------------------------------
311   This register holds the upper nine bits
312   [23:15] of the 24-bit Wlan hardware memory
313   address for burst reads from EEPROM accesses.
314   The EEPROM provides the lower 15 bits of this address.
315   The MSB of the address from the EEPROM is ignored.
316   ===============================================*/
317 #define ACX_EE_CFG                          EE_CFG
318 
319 /*===============================================
320   GPIO Output Values  -32bit, RW
321   ------------------------------------------
322   [31:16]  Reserved
323   [15: 0]  Specify the output values (at the output driver inputs) for
324   GPIO[15:0], respectively.
325   ===============================================*/
326 #define ACX_GPIO_OUT_REG            GPIO_OUT
327 #define ACX_MAX_GPIO_LINES          15
328 
329 /*===============================================
330   Contention window  -32bit, RW
331   ------------------------------------------
332   [31:26]  Reserved
333   [25:16]  Max (0x3ff)
334   [15:07]  Reserved
335   [06:00]  Current contention window value - default is 0x1F
336   ===============================================*/
337 #define ACX_CONT_WIND_CFG_REG    CONT_WIND_CFG
338 #define ACX_CONT_WIND_MIN_MASK   0x0000007f
339 #define ACX_CONT_WIND_MAX        0x03ff0000
340 
341 #define REF_FREQ_19_2                       0
342 #define REF_FREQ_26_0                       1
343 #define REF_FREQ_38_4                       2
344 #define REF_FREQ_40_0                       3
345 #define REF_FREQ_33_6                       4
346 #define REF_FREQ_NUM                        5
347 
348 #define LUT_PARAM_INTEGER_DIVIDER           0
349 #define LUT_PARAM_FRACTIONAL_DIVIDER        1
350 #define LUT_PARAM_ATTN_BB                   2
351 #define LUT_PARAM_ALPHA_BB                  3
352 #define LUT_PARAM_STOP_TIME_BB              4
353 #define LUT_PARAM_BB_PLL_LOOP_FILTER        5
354 #define LUT_PARAM_NUM                       6
355 
356 #define WL12XX_EEPROMLESS_IND		(WL12XX_SCR_PAD4)
357 #define USE_EEPROM                          0
358 #define NVS_DATA_BUNDARY_ALIGNMENT          4
359 
360 /* Firmware image header size */
361 #define FW_HDR_SIZE 8
362 
363 /******************************************************************************
364 
365     CHANNELS, BAND & REG DOMAINS definitions
366 
367 ******************************************************************************/
368 
369 #define SHORT_PREAMBLE_BIT   BIT(0) /* CCK or Barker depending on the rate */
370 #define OFDM_RATE_BIT        BIT(6)
371 #define PBCC_RATE_BIT        BIT(7)
372 
373 enum {
374 	CCK_LONG = 0,
375 	CCK_SHORT = SHORT_PREAMBLE_BIT,
376 	PBCC_LONG = PBCC_RATE_BIT,
377 	PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
378 	OFDM = OFDM_RATE_BIT
379 };
380 
381 /******************************************************************************
382 
383 Transmit-Descriptor RATE-SET field definitions...
384 
385 Define a new "Rate-Set" for TX path that incorporates the
386 Rate & Modulation info into a single 16-bit field.
387 
388 TxdRateSet_t:
389 b15   - Indicates Preamble type (1=SHORT, 0=LONG).
390 	Notes:
391 	Must be LONG (0) for 1Mbps rate.
392 	Does not apply (set to 0) for RevG-OFDM rates.
393 b14   - Indicates PBCC encoding (1=PBCC, 0=not).
394 	Notes:
395 	Does not apply (set to 0) for rates 1 and 2 Mbps.
396 	Does not apply (set to 0) for RevG-OFDM rates.
397 b13    - Unused (set to 0).
398 b12-b0 - Supported Rate indicator bits as defined below.
399 
400 ******************************************************************************/
401 
402 #define OCP_CMD_LOOP		32
403 #define OCP_CMD_WRITE		0x1
404 #define OCP_CMD_READ		0x2
405 #define OCP_READY_MASK		BIT(18)
406 #define OCP_STATUS_MASK		(BIT(16) | BIT(17))
407 #define OCP_STATUS_NO_RESP	0x00000
408 #define OCP_STATUS_OK		0x10000
409 #define OCP_STATUS_REQ_FAILED	0x20000
410 #define OCP_STATUS_RESP_ERROR	0x30000
411 
412 #define OCP_REG_POLARITY     0x0064
413 #define OCP_REG_CLK_TYPE     0x0448
414 #define OCP_REG_CLK_POLARITY 0x0cb2
415 #define OCP_REG_CLK_PULL     0x0cb4
416 
417 #define POLARITY_LOW         BIT(1)
418 #define NO_PULL              (BIT(14) | BIT(15))
419 
420 #define FREF_CLK_TYPE_BITS     0xfffffe7f
421 #define CLK_REQ_PRCM           0x100
422 #define FREF_CLK_POLARITY_BITS 0xfffff8ff
423 #define CLK_REQ_OUTN_SEL       0x700
424 
425 #define WU_COUNTER_PAUSE_VAL 0x3FF
426 
427 /* PLL configuration algorithm for wl128x */
428 #define SYS_CLK_CFG_REG              0x2200
429 /* Bit[0]   -  0-TCXO,  1-FREF */
430 #define MCS_PLL_CLK_SEL_FREF         BIT(0)
431 /* Bit[3:2] - 01-TCXO, 10-FREF */
432 #define WL_CLK_REQ_TYPE_FREF         BIT(3)
433 #define WL_CLK_REQ_TYPE_PG2          (BIT(3) | BIT(2))
434 /* Bit[4]   -  0-TCXO,  1-FREF */
435 #define PRCM_CM_EN_MUX_WLAN_FREF     BIT(4)
436 
437 #define TCXO_ILOAD_INT_REG           0x2264
438 #define TCXO_CLK_DETECT_REG          0x2266
439 
440 #define TCXO_DET_FAILED              BIT(4)
441 
442 #define FREF_ILOAD_INT_REG           0x2084
443 #define FREF_CLK_DETECT_REG          0x2086
444 #define FREF_CLK_DETECT_FAIL         BIT(4)
445 
446 /* Use this reg for masking during driver access */
447 #define WL_SPARE_REG                 0x2320
448 #define WL_SPARE_VAL                 BIT(2)
449 /* Bit[6:5:3] -  mask wl write SYS_CLK_CFG[8:5:2:4] */
450 #define WL_SPARE_MASK_8526           (BIT(6) | BIT(5) | BIT(3))
451 
452 #define PLL_LOCK_COUNTERS_REG        0xD8C
453 #define PLL_LOCK_COUNTERS_COEX       0x0F
454 #define PLL_LOCK_COUNTERS_MCS        0xF0
455 #define MCS_PLL_OVERRIDE_REG         0xD90
456 #define MCS_PLL_CONFIG_REG           0xD92
457 #define MCS_SEL_IN_FREQ_MASK         0x0070
458 #define MCS_SEL_IN_FREQ_SHIFT        4
459 #define MCS_PLL_CONFIG_REG_VAL       0x73
460 #define MCS_PLL_ENABLE_HP            (BIT(0) | BIT(1))
461 
462 #define MCS_PLL_M_REG                0xD94
463 #define MCS_PLL_N_REG                0xD96
464 #define MCS_PLL_M_REG_VAL            0xC8
465 #define MCS_PLL_N_REG_VAL            0x07
466 
467 #define SDIO_IO_DS                   0xd14
468 
469 /* SDIO/wSPI DS configuration values */
470 enum {
471 	HCI_IO_DS_8MA = 0,
472 	HCI_IO_DS_4MA = 1, /* default */
473 	HCI_IO_DS_6MA = 2,
474 	HCI_IO_DS_2MA = 3,
475 };
476 
477 /* end PLL configuration algorithm for wl128x */
478 
479 /*
480  * Host Command Interrupt. Setting this bit masks
481  * the interrupt that the host issues to inform
482  * the FW that it has sent a command
483  * to the Wlan hardware Command Mailbox.
484  */
485 #define WL12XX_INTR_TRIG_CMD		BIT(0)
486 
487 /*
488  * Host Event Acknowlegde Interrupt. The host
489  * sets this bit to acknowledge that it received
490  * the unsolicited information from the event
491  * mailbox.
492  */
493 #define WL12XX_INTR_TRIG_EVENT_ACK	BIT(1)
494 
495 /*===============================================
496   HI_CFG Interface Configuration Register Values
497   ------------------------------------------
498   ===============================================*/
499 #define HI_CFG_UART_ENABLE          0x00000004
500 #define HI_CFG_RST232_ENABLE        0x00000008
501 #define HI_CFG_CLOCK_REQ_SELECT     0x00000010
502 #define HI_CFG_HOST_INT_ENABLE      0x00000020
503 #define HI_CFG_VLYNQ_OUTPUT_ENABLE  0x00000040
504 #define HI_CFG_HOST_INT_ACTIVE_LOW  0x00000080
505 #define HI_CFG_UART_TX_OUT_GPIO_15  0x00000100
506 #define HI_CFG_UART_TX_OUT_GPIO_14  0x00000200
507 #define HI_CFG_UART_TX_OUT_GPIO_7   0x00000400
508 
509 #define HI_CFG_DEF_VAL              \
510 	(HI_CFG_UART_ENABLE |        \
511 	HI_CFG_RST232_ENABLE |      \
512 	HI_CFG_CLOCK_REQ_SELECT |   \
513 	HI_CFG_HOST_INT_ENABLE)
514 
515 #define WL127X_REG_FUSE_DATA_2_1	0x050a
516 #define WL128X_REG_FUSE_DATA_2_1	0x2152
517 #define PG_VER_MASK			0x3c
518 #define PG_VER_OFFSET			2
519 
520 #define WL127X_PG_MAJOR_VER_MASK	0x3
521 #define WL127X_PG_MAJOR_VER_OFFSET	0x0
522 #define WL127X_PG_MINOR_VER_MASK	0xc
523 #define WL127X_PG_MINOR_VER_OFFSET	0x2
524 
525 #define WL128X_PG_MAJOR_VER_MASK	0xc
526 #define WL128X_PG_MAJOR_VER_OFFSET	0x2
527 #define WL128X_PG_MINOR_VER_MASK	0x3
528 #define WL128X_PG_MINOR_VER_OFFSET	0x0
529 
530 #define WL127X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL127X_PG_MAJOR_VER_MASK) >> \
531 				     WL127X_PG_MAJOR_VER_OFFSET)
532 #define WL127X_PG_GET_MINOR(pg_ver) ((pg_ver & WL127X_PG_MINOR_VER_MASK) >> \
533 				     WL127X_PG_MINOR_VER_OFFSET)
534 #define WL128X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL128X_PG_MAJOR_VER_MASK) >> \
535 				     WL128X_PG_MAJOR_VER_OFFSET)
536 #define WL128X_PG_GET_MINOR(pg_ver) ((pg_ver & WL128X_PG_MINOR_VER_MASK) >> \
537 				     WL128X_PG_MINOR_VER_OFFSET)
538 
539 #define WL12XX_REG_FUSE_BD_ADDR_1	0x00310eb4
540 #define WL12XX_REG_FUSE_BD_ADDR_2	0x00310eb8
541 
542 #endif
543