1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
4
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/device.h>
9 #include <linux/wait.h>
10 #include <linux/bitops.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/slimbus.h>
16 #include <sound/soc.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc-dapm.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <sound/tlv.h>
23 #include <sound/info.h>
24 #include "wcd9335.h"
25 #include "wcd-clsh-v2.h"
26
27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
28 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
29 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
30 /* Fractional Rates */
31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
33 SNDRV_PCM_FMTBIT_S24_LE)
34
35 /* slave port water mark level
36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
37 */
38 #define SLAVE_PORT_WATER_MARK_6BYTES 0
39 #define SLAVE_PORT_WATER_MARK_9BYTES 1
40 #define SLAVE_PORT_WATER_MARK_12BYTES 2
41 #define SLAVE_PORT_WATER_MARK_15BYTES 3
42 #define SLAVE_PORT_WATER_MARK_SHIFT 1
43 #define SLAVE_PORT_ENABLE 1
44 #define SLAVE_PORT_DISABLE 0
45 #define WCD9335_SLIM_WATER_MARK_VAL \
46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
47 (SLAVE_PORT_ENABLE))
48
49 #define WCD9335_SLIM_NUM_PORT_REG 3
50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
51
52 #define WCD9335_MCLK_CLK_12P288MHZ 12288000
53 #define WCD9335_MCLK_CLK_9P6MHZ 9600000
54
55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
59
60 #define WCD9335_NUM_INTERPOLATORS 9
61 #define WCD9335_RX_START 16
62 #define WCD9335_SLIM_CH_START 128
63 #define WCD9335_MAX_MICBIAS 4
64 #define WCD9335_MAX_VALID_ADC_MUX 13
65 #define WCD9335_INVALID_ADC_MUX 9
66
67 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
68 #define CF_MIN_3DB_4HZ 0x0
69 #define CF_MIN_3DB_75HZ 0x1
70 #define CF_MIN_3DB_150HZ 0x2
71 #define WCD9335_DMIC_CLK_DIV_2 0x0
72 #define WCD9335_DMIC_CLK_DIV_3 0x1
73 #define WCD9335_DMIC_CLK_DIV_4 0x2
74 #define WCD9335_DMIC_CLK_DIV_6 0x3
75 #define WCD9335_DMIC_CLK_DIV_8 0x4
76 #define WCD9335_DMIC_CLK_DIV_16 0x5
77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
78 #define WCD9335_AMIC_PWR_LEVEL_LP 0
79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
80 #define WCD9335_AMIC_PWR_LEVEL_HP 2
81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
83
84 #define WCD9335_DEC_PWR_LVL_MASK 0x06
85 #define WCD9335_DEC_PWR_LVL_LP 0x02
86 #define WCD9335_DEC_PWR_LVL_HP 0x04
87 #define WCD9335_DEC_PWR_LVL_DF 0x00
88
89 #define WCD9335_SLIM_RX_CH(p) \
90 {.port = p + WCD9335_RX_START, .shift = p,}
91
92 #define WCD9335_SLIM_TX_CH(p) \
93 {.port = p, .shift = p,}
94
95 /* vout step value */
96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
97
98 #define WCD9335_INTERPOLATOR_PATH(id) \
99 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
100 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
101 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
102 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
103 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
104 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
105 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
106 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
107 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
108 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
109 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
110 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
111 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
112 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
113 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
114 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
115 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
116 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
117 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
118 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
119 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
120 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
121 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
122 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
123 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
124 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
125 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
126 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
127 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
128 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
129 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
130 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
131 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
132 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
134 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
135 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
136 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
137 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
138
139 #define WCD9335_ADC_MUX_PATH(id) \
140 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
141 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
142 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
143 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
144 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
145 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
146 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
147 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
148 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
149 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
150 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
151 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
152 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
153 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
154 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
155 {"AMIC MUX" #id, "ADC4", "ADC4"}, \
156 {"AMIC MUX" #id, "ADC5", "ADC5"}, \
157 {"AMIC MUX" #id, "ADC6", "ADC6"}
158
159 enum {
160 WCD9335_RX0 = 0,
161 WCD9335_RX1,
162 WCD9335_RX2,
163 WCD9335_RX3,
164 WCD9335_RX4,
165 WCD9335_RX5,
166 WCD9335_RX6,
167 WCD9335_RX7,
168 WCD9335_RX8,
169 WCD9335_RX9,
170 WCD9335_RX10,
171 WCD9335_RX11,
172 WCD9335_RX12,
173 WCD9335_RX_MAX,
174 };
175
176 enum {
177 WCD9335_TX0 = 0,
178 WCD9335_TX1,
179 WCD9335_TX2,
180 WCD9335_TX3,
181 WCD9335_TX4,
182 WCD9335_TX5,
183 WCD9335_TX6,
184 WCD9335_TX7,
185 WCD9335_TX8,
186 WCD9335_TX9,
187 WCD9335_TX10,
188 WCD9335_TX11,
189 WCD9335_TX12,
190 WCD9335_TX13,
191 WCD9335_TX14,
192 WCD9335_TX15,
193 WCD9335_TX_MAX,
194 };
195
196 enum {
197 SIDO_SOURCE_INTERNAL = 0,
198 SIDO_SOURCE_RCO_BG,
199 };
200
201 enum wcd9335_sido_voltage {
202 SIDO_VOLTAGE_SVS_MV = 950,
203 SIDO_VOLTAGE_NOMINAL_MV = 1100,
204 };
205
206 enum {
207 AIF1_PB = 0,
208 AIF1_CAP,
209 AIF2_PB,
210 AIF2_CAP,
211 AIF3_PB,
212 AIF3_CAP,
213 AIF4_PB,
214 NUM_CODEC_DAIS,
215 };
216
217 enum {
218 COMPANDER_1, /* HPH_L */
219 COMPANDER_2, /* HPH_R */
220 COMPANDER_3, /* LO1_DIFF */
221 COMPANDER_4, /* LO2_DIFF */
222 COMPANDER_5, /* LO3_SE */
223 COMPANDER_6, /* LO4_SE */
224 COMPANDER_7, /* SWR SPK CH1 */
225 COMPANDER_8, /* SWR SPK CH2 */
226 COMPANDER_MAX,
227 };
228
229 enum {
230 INTn_2_INP_SEL_ZERO = 0,
231 INTn_2_INP_SEL_RX0,
232 INTn_2_INP_SEL_RX1,
233 INTn_2_INP_SEL_RX2,
234 INTn_2_INP_SEL_RX3,
235 INTn_2_INP_SEL_RX4,
236 INTn_2_INP_SEL_RX5,
237 INTn_2_INP_SEL_RX6,
238 INTn_2_INP_SEL_RX7,
239 INTn_2_INP_SEL_PROXIMITY,
240 };
241
242 enum {
243 INTn_1_MIX_INP_SEL_ZERO = 0,
244 INTn_1_MIX_INP_SEL_DEC0,
245 INTn_1_MIX_INP_SEL_DEC1,
246 INTn_1_MIX_INP_SEL_IIR0,
247 INTn_1_MIX_INP_SEL_IIR1,
248 INTn_1_MIX_INP_SEL_RX0,
249 INTn_1_MIX_INP_SEL_RX1,
250 INTn_1_MIX_INP_SEL_RX2,
251 INTn_1_MIX_INP_SEL_RX3,
252 INTn_1_MIX_INP_SEL_RX4,
253 INTn_1_MIX_INP_SEL_RX5,
254 INTn_1_MIX_INP_SEL_RX6,
255 INTn_1_MIX_INP_SEL_RX7,
256
257 };
258
259 enum {
260 INTERP_EAR = 0,
261 INTERP_HPHL,
262 INTERP_HPHR,
263 INTERP_LO1,
264 INTERP_LO2,
265 INTERP_LO3,
266 INTERP_LO4,
267 INTERP_SPKR1,
268 INTERP_SPKR2,
269 };
270
271 enum wcd_clock_type {
272 WCD_CLK_OFF,
273 WCD_CLK_RCO,
274 WCD_CLK_MCLK,
275 };
276
277 enum {
278 MIC_BIAS_1 = 1,
279 MIC_BIAS_2,
280 MIC_BIAS_3,
281 MIC_BIAS_4
282 };
283
284 enum {
285 MICB_PULLUP_ENABLE,
286 MICB_PULLUP_DISABLE,
287 MICB_ENABLE,
288 MICB_DISABLE,
289 };
290
291 struct wcd9335_slim_ch {
292 u32 ch_num;
293 u16 port;
294 u16 shift;
295 struct list_head list;
296 };
297
298 struct wcd_slim_codec_dai_data {
299 struct list_head slim_ch_list;
300 struct slim_stream_config sconfig;
301 struct slim_stream_runtime *sruntime;
302 };
303
304 struct wcd9335_codec {
305 struct device *dev;
306 struct clk *mclk;
307 struct clk *native_clk;
308 u32 mclk_rate;
309 u8 version;
310
311 struct slim_device *slim;
312 struct slim_device *slim_ifc_dev;
313 struct regmap *regmap;
314 struct regmap *if_regmap;
315 struct regmap_irq_chip_data *irq_data;
316
317 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
318 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
319 u32 num_rx_port;
320 u32 num_tx_port;
321
322 int sido_input_src;
323 enum wcd9335_sido_voltage sido_voltage;
324
325 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
326 struct snd_soc_component *component;
327
328 int master_bias_users;
329 int clk_mclk_users;
330 int clk_rco_users;
331 int sido_ccl_cnt;
332 enum wcd_clock_type clk_type;
333
334 struct wcd_clsh_ctrl *clsh_ctrl;
335 u32 hph_mode;
336 int prim_int_users[WCD9335_NUM_INTERPOLATORS];
337
338 int comp_enabled[COMPANDER_MAX];
339
340 int intr1;
341 int reset_gpio;
342 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
343
344 unsigned int rx_port_value[WCD9335_RX_MAX];
345 unsigned int tx_port_value[WCD9335_TX_MAX];
346 int hph_l_gain;
347 int hph_r_gain;
348 u32 rx_bias_count;
349
350 /*TX*/
351 int micb_ref[WCD9335_MAX_MICBIAS];
352 int pullup_ref[WCD9335_MAX_MICBIAS];
353
354 int dmic_0_1_clk_cnt;
355 int dmic_2_3_clk_cnt;
356 int dmic_4_5_clk_cnt;
357 int dmic_sample_rate;
358 int mad_dmic_sample_rate;
359
360 int native_clk_users;
361 };
362
363 struct wcd9335_irq {
364 int irq;
365 irqreturn_t (*handler)(int irq, void *data);
366 char *name;
367 };
368
369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
370 WCD9335_SLIM_TX_CH(0),
371 WCD9335_SLIM_TX_CH(1),
372 WCD9335_SLIM_TX_CH(2),
373 WCD9335_SLIM_TX_CH(3),
374 WCD9335_SLIM_TX_CH(4),
375 WCD9335_SLIM_TX_CH(5),
376 WCD9335_SLIM_TX_CH(6),
377 WCD9335_SLIM_TX_CH(7),
378 WCD9335_SLIM_TX_CH(8),
379 WCD9335_SLIM_TX_CH(9),
380 WCD9335_SLIM_TX_CH(10),
381 WCD9335_SLIM_TX_CH(11),
382 WCD9335_SLIM_TX_CH(12),
383 WCD9335_SLIM_TX_CH(13),
384 WCD9335_SLIM_TX_CH(14),
385 WCD9335_SLIM_TX_CH(15),
386 };
387
388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
389 WCD9335_SLIM_RX_CH(0), /* 16 */
390 WCD9335_SLIM_RX_CH(1), /* 17 */
391 WCD9335_SLIM_RX_CH(2),
392 WCD9335_SLIM_RX_CH(3),
393 WCD9335_SLIM_RX_CH(4),
394 WCD9335_SLIM_RX_CH(5),
395 WCD9335_SLIM_RX_CH(6),
396 WCD9335_SLIM_RX_CH(7),
397 WCD9335_SLIM_RX_CH(8),
398 WCD9335_SLIM_RX_CH(9),
399 WCD9335_SLIM_RX_CH(10),
400 WCD9335_SLIM_RX_CH(11),
401 WCD9335_SLIM_RX_CH(12),
402 };
403
404 struct interp_sample_rate {
405 int rate;
406 int rate_val;
407 };
408
409 static struct interp_sample_rate int_mix_rate_val[] = {
410 {48000, 0x4}, /* 48K */
411 {96000, 0x5}, /* 96K */
412 {192000, 0x6}, /* 192K */
413 };
414
415 static struct interp_sample_rate int_prim_rate_val[] = {
416 {8000, 0x0}, /* 8K */
417 {16000, 0x1}, /* 16K */
418 {24000, -EINVAL},/* 24K */
419 {32000, 0x3}, /* 32K */
420 {48000, 0x4}, /* 48K */
421 {96000, 0x5}, /* 96K */
422 {192000, 0x6}, /* 192K */
423 {384000, 0x7}, /* 384K */
424 {44100, 0x8}, /* 44.1K */
425 };
426
427 struct wcd9335_reg_mask_val {
428 u16 reg;
429 u8 mask;
430 u8 val;
431 };
432
433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
434 /* Rbuckfly/R_EAR(32) */
435 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
436 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
437 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
438 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
439 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
440 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
441 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
442 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
443 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
444 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
445 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
446 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
447 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
448 {WCD9335_EAR_CMBUFF, 0x08, 0x00},
449 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
450 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
451 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
452 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
453 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
454 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
455 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
456 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
457 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
458 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
459 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
460 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
461 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
462 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
463 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
464 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
465 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
466 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
467 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
468 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
469 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
470 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
471 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
472 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
473 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
474 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
475 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
476 {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
477 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
478 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
479 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
480 {WCD9335_HPH_L_TEST, 0x01, 0x01},
481 {WCD9335_HPH_R_TEST, 0x01, 0x01},
482 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
483 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
484 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
485 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
486 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
487 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
488 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
489 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
490 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
491 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
492 };
493
494 /* Cutoff frequency for high pass filter */
495 static const char * const cf_text[] = {
496 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
497 };
498
499 static const char * const rx_cf_text[] = {
500 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
501 "CF_NEG_3DB_0P48HZ"
502 };
503
504 static const char * const rx_int0_7_mix_mux_text[] = {
505 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
506 "RX6", "RX7", "PROXIMITY"
507 };
508
509 static const char * const rx_int_mix_mux_text[] = {
510 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
511 "RX6", "RX7"
512 };
513
514 static const char * const rx_prim_mix_text[] = {
515 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
516 "RX3", "RX4", "RX5", "RX6", "RX7"
517 };
518
519 static const char * const rx_int_dem_inp_mux_text[] = {
520 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
521 };
522
523 static const char * const rx_int0_interp_mux_text[] = {
524 "ZERO", "RX INT0 MIX2",
525 };
526
527 static const char * const rx_int1_interp_mux_text[] = {
528 "ZERO", "RX INT1 MIX2",
529 };
530
531 static const char * const rx_int2_interp_mux_text[] = {
532 "ZERO", "RX INT2 MIX2",
533 };
534
535 static const char * const rx_int3_interp_mux_text[] = {
536 "ZERO", "RX INT3 MIX2",
537 };
538
539 static const char * const rx_int4_interp_mux_text[] = {
540 "ZERO", "RX INT4 MIX2",
541 };
542
543 static const char * const rx_int5_interp_mux_text[] = {
544 "ZERO", "RX INT5 MIX2",
545 };
546
547 static const char * const rx_int6_interp_mux_text[] = {
548 "ZERO", "RX INT6 MIX2",
549 };
550
551 static const char * const rx_int7_interp_mux_text[] = {
552 "ZERO", "RX INT7 MIX2",
553 };
554
555 static const char * const rx_int8_interp_mux_text[] = {
556 "ZERO", "RX INT8 SEC MIX"
557 };
558
559 static const char * const rx_hph_mode_mux_text[] = {
560 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
561 "Class-H Hi-Fi Low Power"
562 };
563
564 static const char *const slim_rx_mux_text[] = {
565 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
566 };
567
568 static const char * const adc_mux_text[] = {
569 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
570 };
571
572 static const char * const dmic_mux_text[] = {
573 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
574 "SMIC0", "SMIC1", "SMIC2", "SMIC3"
575 };
576
577 static const char * const dmic_mux_alt_text[] = {
578 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
579 };
580
581 static const char * const amic_mux_text[] = {
582 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
583 };
584
585 static const char * const sb_tx0_mux_text[] = {
586 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
587 };
588
589 static const char * const sb_tx1_mux_text[] = {
590 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
591 };
592
593 static const char * const sb_tx2_mux_text[] = {
594 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
595 };
596
597 static const char * const sb_tx3_mux_text[] = {
598 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
599 };
600
601 static const char * const sb_tx4_mux_text[] = {
602 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
603 };
604
605 static const char * const sb_tx5_mux_text[] = {
606 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
607 };
608
609 static const char * const sb_tx6_mux_text[] = {
610 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
611 };
612
613 static const char * const sb_tx7_mux_text[] = {
614 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
615 };
616
617 static const char * const sb_tx8_mux_text[] = {
618 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
619 };
620
621 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
625
626 static const struct soc_enum cf_dec0_enum =
627 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
628
629 static const struct soc_enum cf_dec1_enum =
630 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
631
632 static const struct soc_enum cf_dec2_enum =
633 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
634
635 static const struct soc_enum cf_dec3_enum =
636 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
637
638 static const struct soc_enum cf_dec4_enum =
639 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
640
641 static const struct soc_enum cf_dec5_enum =
642 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
643
644 static const struct soc_enum cf_dec6_enum =
645 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
646
647 static const struct soc_enum cf_dec7_enum =
648 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
649
650 static const struct soc_enum cf_dec8_enum =
651 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
652
653 static const struct soc_enum cf_int0_1_enum =
654 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
655
656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
657 rx_cf_text);
658
659 static const struct soc_enum cf_int1_1_enum =
660 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
661
662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
663 rx_cf_text);
664
665 static const struct soc_enum cf_int2_1_enum =
666 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
667
668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
669 rx_cf_text);
670
671 static const struct soc_enum cf_int3_1_enum =
672 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
673
674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
675 rx_cf_text);
676
677 static const struct soc_enum cf_int4_1_enum =
678 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
679
680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
681 rx_cf_text);
682
683 static const struct soc_enum cf_int5_1_enum =
684 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
685
686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
687 rx_cf_text);
688
689 static const struct soc_enum cf_int6_1_enum =
690 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
691
692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
693 rx_cf_text);
694
695 static const struct soc_enum cf_int7_1_enum =
696 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
697
698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
699 rx_cf_text);
700
701 static const struct soc_enum cf_int8_1_enum =
702 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
703
704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
705 rx_cf_text);
706
707 static const struct soc_enum rx_hph_mode_mux_enum =
708 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
709 rx_hph_mode_mux_text);
710
711 static const struct soc_enum slim_rx_mux_enum =
712 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
713
714 static const struct soc_enum rx_int0_2_mux_chain_enum =
715 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
716 rx_int0_7_mix_mux_text);
717
718 static const struct soc_enum rx_int1_2_mux_chain_enum =
719 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
720 rx_int_mix_mux_text);
721
722 static const struct soc_enum rx_int2_2_mux_chain_enum =
723 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
724 rx_int_mix_mux_text);
725
726 static const struct soc_enum rx_int3_2_mux_chain_enum =
727 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
728 rx_int_mix_mux_text);
729
730 static const struct soc_enum rx_int4_2_mux_chain_enum =
731 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
732 rx_int_mix_mux_text);
733
734 static const struct soc_enum rx_int5_2_mux_chain_enum =
735 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
736 rx_int_mix_mux_text);
737
738 static const struct soc_enum rx_int6_2_mux_chain_enum =
739 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
740 rx_int_mix_mux_text);
741
742 static const struct soc_enum rx_int7_2_mux_chain_enum =
743 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
744 rx_int0_7_mix_mux_text);
745
746 static const struct soc_enum rx_int8_2_mux_chain_enum =
747 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
748 rx_int_mix_mux_text);
749
750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
751 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
752 rx_prim_mix_text);
753
754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
755 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
756 rx_prim_mix_text);
757
758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
759 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
760 rx_prim_mix_text);
761
762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
763 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
764 rx_prim_mix_text);
765
766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
767 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
768 rx_prim_mix_text);
769
770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
771 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
772 rx_prim_mix_text);
773
774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
775 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
776 rx_prim_mix_text);
777
778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
779 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
780 rx_prim_mix_text);
781
782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
783 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
784 rx_prim_mix_text);
785
786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
787 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
788 rx_prim_mix_text);
789
790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
791 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
792 rx_prim_mix_text);
793
794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
795 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
796 rx_prim_mix_text);
797
798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
799 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
800 rx_prim_mix_text);
801
802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
803 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
804 rx_prim_mix_text);
805
806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
807 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
808 rx_prim_mix_text);
809
810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
811 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
812 rx_prim_mix_text);
813
814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
815 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
816 rx_prim_mix_text);
817
818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
819 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
820 rx_prim_mix_text);
821
822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
823 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
824 rx_prim_mix_text);
825
826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
827 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
828 rx_prim_mix_text);
829
830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
831 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
832 rx_prim_mix_text);
833
834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
835 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
836 rx_prim_mix_text);
837
838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
839 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
840 rx_prim_mix_text);
841
842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
843 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
844 rx_prim_mix_text);
845
846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
847 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
848 rx_prim_mix_text);
849
850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
851 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
852 rx_prim_mix_text);
853
854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
855 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
856 rx_prim_mix_text);
857
858 static const struct soc_enum rx_int0_dem_inp_mux_enum =
859 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
860 ARRAY_SIZE(rx_int_dem_inp_mux_text),
861 rx_int_dem_inp_mux_text);
862
863 static const struct soc_enum rx_int1_dem_inp_mux_enum =
864 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
865 ARRAY_SIZE(rx_int_dem_inp_mux_text),
866 rx_int_dem_inp_mux_text);
867
868 static const struct soc_enum rx_int2_dem_inp_mux_enum =
869 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
870 ARRAY_SIZE(rx_int_dem_inp_mux_text),
871 rx_int_dem_inp_mux_text);
872
873 static const struct soc_enum rx_int0_interp_mux_enum =
874 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
875 rx_int0_interp_mux_text);
876
877 static const struct soc_enum rx_int1_interp_mux_enum =
878 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
879 rx_int1_interp_mux_text);
880
881 static const struct soc_enum rx_int2_interp_mux_enum =
882 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
883 rx_int2_interp_mux_text);
884
885 static const struct soc_enum rx_int3_interp_mux_enum =
886 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
887 rx_int3_interp_mux_text);
888
889 static const struct soc_enum rx_int4_interp_mux_enum =
890 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
891 rx_int4_interp_mux_text);
892
893 static const struct soc_enum rx_int5_interp_mux_enum =
894 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
895 rx_int5_interp_mux_text);
896
897 static const struct soc_enum rx_int6_interp_mux_enum =
898 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
899 rx_int6_interp_mux_text);
900
901 static const struct soc_enum rx_int7_interp_mux_enum =
902 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
903 rx_int7_interp_mux_text);
904
905 static const struct soc_enum rx_int8_interp_mux_enum =
906 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
907 rx_int8_interp_mux_text);
908
909 static const struct soc_enum tx_adc_mux0_chain_enum =
910 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
911 adc_mux_text);
912
913 static const struct soc_enum tx_adc_mux1_chain_enum =
914 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
915 adc_mux_text);
916
917 static const struct soc_enum tx_adc_mux2_chain_enum =
918 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
919 adc_mux_text);
920
921 static const struct soc_enum tx_adc_mux3_chain_enum =
922 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
923 adc_mux_text);
924
925 static const struct soc_enum tx_adc_mux4_chain_enum =
926 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
927 adc_mux_text);
928
929 static const struct soc_enum tx_adc_mux5_chain_enum =
930 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
931 adc_mux_text);
932
933 static const struct soc_enum tx_adc_mux6_chain_enum =
934 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
935 adc_mux_text);
936
937 static const struct soc_enum tx_adc_mux7_chain_enum =
938 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
939 adc_mux_text);
940
941 static const struct soc_enum tx_adc_mux8_chain_enum =
942 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
943 adc_mux_text);
944
945 static const struct soc_enum tx_dmic_mux0_enum =
946 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
947 dmic_mux_text);
948
949 static const struct soc_enum tx_dmic_mux1_enum =
950 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
951 dmic_mux_text);
952
953 static const struct soc_enum tx_dmic_mux2_enum =
954 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
955 dmic_mux_text);
956
957 static const struct soc_enum tx_dmic_mux3_enum =
958 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
959 dmic_mux_text);
960
961 static const struct soc_enum tx_dmic_mux4_enum =
962 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
963 dmic_mux_alt_text);
964
965 static const struct soc_enum tx_dmic_mux5_enum =
966 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
967 dmic_mux_alt_text);
968
969 static const struct soc_enum tx_dmic_mux6_enum =
970 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
971 dmic_mux_alt_text);
972
973 static const struct soc_enum tx_dmic_mux7_enum =
974 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
975 dmic_mux_alt_text);
976
977 static const struct soc_enum tx_dmic_mux8_enum =
978 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
979 dmic_mux_alt_text);
980
981 static const struct soc_enum tx_amic_mux0_enum =
982 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
983 amic_mux_text);
984
985 static const struct soc_enum tx_amic_mux1_enum =
986 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
987 amic_mux_text);
988
989 static const struct soc_enum tx_amic_mux2_enum =
990 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
991 amic_mux_text);
992
993 static const struct soc_enum tx_amic_mux3_enum =
994 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
995 amic_mux_text);
996
997 static const struct soc_enum tx_amic_mux4_enum =
998 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
999 amic_mux_text);
1000
1001 static const struct soc_enum tx_amic_mux5_enum =
1002 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
1003 amic_mux_text);
1004
1005 static const struct soc_enum tx_amic_mux6_enum =
1006 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
1007 amic_mux_text);
1008
1009 static const struct soc_enum tx_amic_mux7_enum =
1010 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1011 amic_mux_text);
1012
1013 static const struct soc_enum tx_amic_mux8_enum =
1014 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1015 amic_mux_text);
1016
1017 static const struct soc_enum sb_tx0_mux_enum =
1018 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1019 sb_tx0_mux_text);
1020
1021 static const struct soc_enum sb_tx1_mux_enum =
1022 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1023 sb_tx1_mux_text);
1024
1025 static const struct soc_enum sb_tx2_mux_enum =
1026 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1027 sb_tx2_mux_text);
1028
1029 static const struct soc_enum sb_tx3_mux_enum =
1030 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1031 sb_tx3_mux_text);
1032
1033 static const struct soc_enum sb_tx4_mux_enum =
1034 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1035 sb_tx4_mux_text);
1036
1037 static const struct soc_enum sb_tx5_mux_enum =
1038 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1039 sb_tx5_mux_text);
1040
1041 static const struct soc_enum sb_tx6_mux_enum =
1042 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1043 sb_tx6_mux_text);
1044
1045 static const struct soc_enum sb_tx7_mux_enum =
1046 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1047 sb_tx7_mux_text);
1048
1049 static const struct soc_enum sb_tx8_mux_enum =
1050 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1051 sb_tx8_mux_text);
1052
1053 static const struct snd_kcontrol_new rx_int0_2_mux =
1054 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1055
1056 static const struct snd_kcontrol_new rx_int1_2_mux =
1057 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1058
1059 static const struct snd_kcontrol_new rx_int2_2_mux =
1060 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1061
1062 static const struct snd_kcontrol_new rx_int3_2_mux =
1063 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1064
1065 static const struct snd_kcontrol_new rx_int4_2_mux =
1066 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1067
1068 static const struct snd_kcontrol_new rx_int5_2_mux =
1069 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1070
1071 static const struct snd_kcontrol_new rx_int6_2_mux =
1072 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1073
1074 static const struct snd_kcontrol_new rx_int7_2_mux =
1075 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1076
1077 static const struct snd_kcontrol_new rx_int8_2_mux =
1078 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1079
1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1081 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1082
1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1084 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1085
1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1087 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1088
1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1090 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1091
1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1093 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1094
1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1096 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1097
1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1099 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1100
1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1102 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1103
1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1105 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1106
1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1108 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1109
1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1111 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1112
1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1114 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1115
1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1117 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1118
1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1120 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1121
1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1123 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1124
1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1126 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1127
1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1129 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1130
1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1132 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1133
1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1135 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1136
1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1138 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1139
1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1141 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1142
1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1144 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1145
1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1147 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1148
1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1150 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1151
1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1153 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1154
1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1156 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1157
1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1159 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1160
1161 static const struct snd_kcontrol_new rx_int0_interp_mux =
1162 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1163
1164 static const struct snd_kcontrol_new rx_int1_interp_mux =
1165 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1166
1167 static const struct snd_kcontrol_new rx_int2_interp_mux =
1168 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1169
1170 static const struct snd_kcontrol_new rx_int3_interp_mux =
1171 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1172
1173 static const struct snd_kcontrol_new rx_int4_interp_mux =
1174 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1175
1176 static const struct snd_kcontrol_new rx_int5_interp_mux =
1177 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1178
1179 static const struct snd_kcontrol_new rx_int6_interp_mux =
1180 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1181
1182 static const struct snd_kcontrol_new rx_int7_interp_mux =
1183 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1184
1185 static const struct snd_kcontrol_new rx_int8_interp_mux =
1186 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1187
1188 static const struct snd_kcontrol_new tx_dmic_mux0 =
1189 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1190
1191 static const struct snd_kcontrol_new tx_dmic_mux1 =
1192 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1193
1194 static const struct snd_kcontrol_new tx_dmic_mux2 =
1195 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1196
1197 static const struct snd_kcontrol_new tx_dmic_mux3 =
1198 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1199
1200 static const struct snd_kcontrol_new tx_dmic_mux4 =
1201 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1202
1203 static const struct snd_kcontrol_new tx_dmic_mux5 =
1204 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1205
1206 static const struct snd_kcontrol_new tx_dmic_mux6 =
1207 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1208
1209 static const struct snd_kcontrol_new tx_dmic_mux7 =
1210 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1211
1212 static const struct snd_kcontrol_new tx_dmic_mux8 =
1213 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1214
1215 static const struct snd_kcontrol_new tx_amic_mux0 =
1216 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1217
1218 static const struct snd_kcontrol_new tx_amic_mux1 =
1219 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1220
1221 static const struct snd_kcontrol_new tx_amic_mux2 =
1222 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1223
1224 static const struct snd_kcontrol_new tx_amic_mux3 =
1225 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1226
1227 static const struct snd_kcontrol_new tx_amic_mux4 =
1228 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1229
1230 static const struct snd_kcontrol_new tx_amic_mux5 =
1231 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1232
1233 static const struct snd_kcontrol_new tx_amic_mux6 =
1234 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1235
1236 static const struct snd_kcontrol_new tx_amic_mux7 =
1237 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1238
1239 static const struct snd_kcontrol_new tx_amic_mux8 =
1240 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1241
1242 static const struct snd_kcontrol_new sb_tx0_mux =
1243 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1244
1245 static const struct snd_kcontrol_new sb_tx1_mux =
1246 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1247
1248 static const struct snd_kcontrol_new sb_tx2_mux =
1249 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1250
1251 static const struct snd_kcontrol_new sb_tx3_mux =
1252 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1253
1254 static const struct snd_kcontrol_new sb_tx4_mux =
1255 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1256
1257 static const struct snd_kcontrol_new sb_tx5_mux =
1258 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1259
1260 static const struct snd_kcontrol_new sb_tx6_mux =
1261 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1262
1263 static const struct snd_kcontrol_new sb_tx7_mux =
1264 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1265
1266 static const struct snd_kcontrol_new sb_tx8_mux =
1267 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1268
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1269 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1270 struct snd_ctl_elem_value *ucontrol)
1271 {
1272 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1273 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1274 u32 port_id = w->shift;
1275
1276 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1277
1278 return 0;
1279 }
1280
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1281 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1282 struct snd_ctl_elem_value *ucontrol)
1283 {
1284 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1285 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1286 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1287 struct snd_soc_dapm_update *update = NULL;
1288 u32 port_id = w->shift;
1289
1290 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1291 return 0;
1292
1293 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1294
1295 /* Remove channel from any list it's in before adding it to a new one */
1296 list_del_init(&wcd->rx_chs[port_id].list);
1297
1298 switch (wcd->rx_port_value[port_id]) {
1299 case 0:
1300 /* Channel already removed from lists. Nothing to do here */
1301 break;
1302 case 1:
1303 list_add_tail(&wcd->rx_chs[port_id].list,
1304 &wcd->dai[AIF1_PB].slim_ch_list);
1305 break;
1306 case 2:
1307 list_add_tail(&wcd->rx_chs[port_id].list,
1308 &wcd->dai[AIF2_PB].slim_ch_list);
1309 break;
1310 case 3:
1311 list_add_tail(&wcd->rx_chs[port_id].list,
1312 &wcd->dai[AIF3_PB].slim_ch_list);
1313 break;
1314 case 4:
1315 list_add_tail(&wcd->rx_chs[port_id].list,
1316 &wcd->dai[AIF4_PB].slim_ch_list);
1317 break;
1318 default:
1319 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1320 goto err;
1321 }
1322
1323 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1324 e, update);
1325
1326 return 0;
1327 err:
1328 return -EINVAL;
1329 }
1330
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1331 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1332 struct snd_ctl_elem_value *ucontrol)
1333 {
1334
1335 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1336 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1337 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1338 struct soc_mixer_control *mixer =
1339 (struct soc_mixer_control *)kc->private_value;
1340 int dai_id = widget->shift;
1341 int port_id = mixer->shift;
1342
1343 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
1344
1345 return 0;
1346 }
1347
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1348 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1349 struct snd_ctl_elem_value *ucontrol)
1350 {
1351
1352 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1353 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1354 struct snd_soc_dapm_update *update = NULL;
1355 struct soc_mixer_control *mixer =
1356 (struct soc_mixer_control *)kc->private_value;
1357 int enable = ucontrol->value.integer.value[0];
1358 int dai_id = widget->shift;
1359 int port_id = mixer->shift;
1360
1361 switch (dai_id) {
1362 case AIF1_CAP:
1363 case AIF2_CAP:
1364 case AIF3_CAP:
1365 /* only add to the list if value not set */
1366 if (enable && wcd->tx_port_value[port_id] != dai_id) {
1367 wcd->tx_port_value[port_id] = dai_id;
1368 list_add_tail(&wcd->tx_chs[port_id].list,
1369 &wcd->dai[dai_id].slim_ch_list);
1370 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
1371 wcd->tx_port_value[port_id] = -1;
1372 list_del_init(&wcd->tx_chs[port_id].list);
1373 }
1374 break;
1375 default:
1376 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1377 return -EINVAL;
1378 }
1379
1380 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1381
1382 return 0;
1383 }
1384
1385 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1386 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1387 slim_rx_mux_get, slim_rx_mux_put),
1388 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1389 slim_rx_mux_get, slim_rx_mux_put),
1390 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1391 slim_rx_mux_get, slim_rx_mux_put),
1392 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1393 slim_rx_mux_get, slim_rx_mux_put),
1394 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1395 slim_rx_mux_get, slim_rx_mux_put),
1396 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1397 slim_rx_mux_get, slim_rx_mux_put),
1398 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1399 slim_rx_mux_get, slim_rx_mux_put),
1400 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1401 slim_rx_mux_get, slim_rx_mux_put),
1402 };
1403
1404 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1405 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1406 slim_tx_mixer_get, slim_tx_mixer_put),
1407 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1408 slim_tx_mixer_get, slim_tx_mixer_put),
1409 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1410 slim_tx_mixer_get, slim_tx_mixer_put),
1411 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1412 slim_tx_mixer_get, slim_tx_mixer_put),
1413 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1414 slim_tx_mixer_get, slim_tx_mixer_put),
1415 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1416 slim_tx_mixer_get, slim_tx_mixer_put),
1417 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1418 slim_tx_mixer_get, slim_tx_mixer_put),
1419 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1420 slim_tx_mixer_get, slim_tx_mixer_put),
1421 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1422 slim_tx_mixer_get, slim_tx_mixer_put),
1423 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1424 slim_tx_mixer_get, slim_tx_mixer_put),
1425 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1426 slim_tx_mixer_get, slim_tx_mixer_put),
1427 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1428 slim_tx_mixer_get, slim_tx_mixer_put),
1429 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1430 slim_tx_mixer_get, slim_tx_mixer_put),
1431 };
1432
1433 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1434 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1435 slim_tx_mixer_get, slim_tx_mixer_put),
1436 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1437 slim_tx_mixer_get, slim_tx_mixer_put),
1438 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1439 slim_tx_mixer_get, slim_tx_mixer_put),
1440 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1441 slim_tx_mixer_get, slim_tx_mixer_put),
1442 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1443 slim_tx_mixer_get, slim_tx_mixer_put),
1444 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1445 slim_tx_mixer_get, slim_tx_mixer_put),
1446 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1447 slim_tx_mixer_get, slim_tx_mixer_put),
1448 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1449 slim_tx_mixer_get, slim_tx_mixer_put),
1450 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1451 slim_tx_mixer_get, slim_tx_mixer_put),
1452 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1453 slim_tx_mixer_get, slim_tx_mixer_put),
1454 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1455 slim_tx_mixer_get, slim_tx_mixer_put),
1456 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1457 slim_tx_mixer_get, slim_tx_mixer_put),
1458 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1459 slim_tx_mixer_get, slim_tx_mixer_put),
1460 };
1461
1462 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1463 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1464 slim_tx_mixer_get, slim_tx_mixer_put),
1465 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1466 slim_tx_mixer_get, slim_tx_mixer_put),
1467 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1468 slim_tx_mixer_get, slim_tx_mixer_put),
1469 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1470 slim_tx_mixer_get, slim_tx_mixer_put),
1471 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1472 slim_tx_mixer_get, slim_tx_mixer_put),
1473 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1474 slim_tx_mixer_get, slim_tx_mixer_put),
1475 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1476 slim_tx_mixer_get, slim_tx_mixer_put),
1477 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1478 slim_tx_mixer_get, slim_tx_mixer_put),
1479 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1480 slim_tx_mixer_get, slim_tx_mixer_put),
1481 };
1482
wcd9335_put_dec_enum(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1483 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1484 struct snd_ctl_elem_value *ucontrol)
1485 {
1486 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1487 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1488 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1489 unsigned int val, reg, sel;
1490
1491 val = ucontrol->value.enumerated.item[0];
1492
1493 switch (e->reg) {
1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1495 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1496 break;
1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1498 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1499 break;
1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1501 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1502 break;
1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1504 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1505 break;
1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1507 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1508 break;
1509 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1510 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1511 break;
1512 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1513 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1514 break;
1515 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1516 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1517 break;
1518 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1519 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1520 break;
1521 default:
1522 return -EINVAL;
1523 }
1524
1525 /* AMIC: 0, DMIC: 1 */
1526 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1527 snd_soc_component_update_bits(component, reg,
1528 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1529 sel);
1530
1531 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1532 }
1533
wcd9335_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1534 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1535 struct snd_ctl_elem_value *ucontrol)
1536 {
1537 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1538 struct snd_soc_component *component;
1539 int reg, val;
1540
1541 component = snd_soc_dapm_kcontrol_component(kc);
1542 val = ucontrol->value.enumerated.item[0];
1543
1544 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1545 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1546 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1547 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1548 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1549 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1550 else
1551 return -EINVAL;
1552
1553 /* Set Look Ahead Delay */
1554 snd_soc_component_update_bits(component, reg,
1555 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1556 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1557 /* Set DEM INP Select */
1558 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1559 }
1560
1561 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1562 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1563 snd_soc_dapm_get_enum_double,
1564 wcd9335_int_dem_inp_mux_put);
1565
1566 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1567 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1568 snd_soc_dapm_get_enum_double,
1569 wcd9335_int_dem_inp_mux_put);
1570
1571 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1572 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1573 snd_soc_dapm_get_enum_double,
1574 wcd9335_int_dem_inp_mux_put);
1575
1576 static const struct snd_kcontrol_new tx_adc_mux0 =
1577 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1578 snd_soc_dapm_get_enum_double,
1579 wcd9335_put_dec_enum);
1580
1581 static const struct snd_kcontrol_new tx_adc_mux1 =
1582 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1583 snd_soc_dapm_get_enum_double,
1584 wcd9335_put_dec_enum);
1585
1586 static const struct snd_kcontrol_new tx_adc_mux2 =
1587 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1588 snd_soc_dapm_get_enum_double,
1589 wcd9335_put_dec_enum);
1590
1591 static const struct snd_kcontrol_new tx_adc_mux3 =
1592 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1593 snd_soc_dapm_get_enum_double,
1594 wcd9335_put_dec_enum);
1595
1596 static const struct snd_kcontrol_new tx_adc_mux4 =
1597 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1598 snd_soc_dapm_get_enum_double,
1599 wcd9335_put_dec_enum);
1600
1601 static const struct snd_kcontrol_new tx_adc_mux5 =
1602 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1603 snd_soc_dapm_get_enum_double,
1604 wcd9335_put_dec_enum);
1605
1606 static const struct snd_kcontrol_new tx_adc_mux6 =
1607 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1608 snd_soc_dapm_get_enum_double,
1609 wcd9335_put_dec_enum);
1610
1611 static const struct snd_kcontrol_new tx_adc_mux7 =
1612 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1613 snd_soc_dapm_get_enum_double,
1614 wcd9335_put_dec_enum);
1615
1616 static const struct snd_kcontrol_new tx_adc_mux8 =
1617 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1618 snd_soc_dapm_get_enum_double,
1619 wcd9335_put_dec_enum);
1620
wcd9335_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1621 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1622 int rate_val,
1623 u32 rate)
1624 {
1625 struct snd_soc_component *component = dai->component;
1626 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1627 struct wcd9335_slim_ch *ch;
1628 int val, j;
1629
1630 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1631 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1632 val = snd_soc_component_read(component,
1633 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1634 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1635
1636 if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1637 snd_soc_component_update_bits(component,
1638 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1639 WCD9335_CDC_MIX_PCM_RATE_MASK,
1640 rate_val);
1641 }
1642 }
1643
1644 return 0;
1645 }
1646
wcd9335_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1647 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1648 u8 rate_val,
1649 u32 rate)
1650 {
1651 struct snd_soc_component *comp = dai->component;
1652 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1653 struct wcd9335_slim_ch *ch;
1654 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1655 int inp, j;
1656
1657 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1658 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1659 /*
1660 * Loop through all interpolator MUX inputs and find out
1661 * to which interpolator input, the slim rx port
1662 * is connected
1663 */
1664 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1665 cfg0 = snd_soc_component_read(comp,
1666 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1667 cfg1 = snd_soc_component_read(comp,
1668 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1669
1670 inp0_sel = cfg0 &
1671 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1672 inp1_sel = (cfg0 >> 4) &
1673 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1674 inp2_sel = (cfg1 >> 4) &
1675 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1676
1677 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1678 (inp2_sel == inp)) {
1679 /* rate is in Hz */
1680 if ((j == 0) && (rate == 44100))
1681 dev_info(wcd->dev,
1682 "Cannot set 44.1KHz on INT0\n");
1683 else
1684 snd_soc_component_update_bits(comp,
1685 WCD9335_CDC_RX_PATH_CTL(j),
1686 WCD9335_CDC_MIX_PCM_RATE_MASK,
1687 rate_val);
1688 }
1689 }
1690 }
1691
1692 return 0;
1693 }
1694
wcd9335_set_interpolator_rate(struct snd_soc_dai * dai,u32 rate)1695 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1696 {
1697 int i;
1698
1699 /* set mixing path rate */
1700 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1701 if (rate == int_mix_rate_val[i].rate) {
1702 wcd9335_set_mix_interpolator_rate(dai,
1703 int_mix_rate_val[i].rate_val, rate);
1704 break;
1705 }
1706 }
1707
1708 /* set primary path sample rate */
1709 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1710 if (rate == int_prim_rate_val[i].rate) {
1711 wcd9335_set_prim_interpolator_rate(dai,
1712 int_prim_rate_val[i].rate_val, rate);
1713 break;
1714 }
1715 }
1716
1717 return 0;
1718 }
1719
wcd9335_slim_set_hw_params(struct wcd9335_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1720 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1721 struct wcd_slim_codec_dai_data *dai_data,
1722 int direction)
1723 {
1724 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1725 struct slim_stream_config *cfg = &dai_data->sconfig;
1726 struct wcd9335_slim_ch *ch;
1727 u16 payload = 0;
1728 int ret, i;
1729
1730 cfg->ch_count = 0;
1731 cfg->direction = direction;
1732 cfg->port_mask = 0;
1733
1734 /* Configure slave interface device */
1735 list_for_each_entry(ch, slim_ch_list, list) {
1736 cfg->ch_count++;
1737 payload |= 1 << ch->shift;
1738 cfg->port_mask |= BIT(ch->port);
1739 }
1740
1741 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1742 if (!cfg->chs)
1743 return -ENOMEM;
1744
1745 i = 0;
1746 list_for_each_entry(ch, slim_ch_list, list) {
1747 cfg->chs[i++] = ch->ch_num;
1748 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1749 /* write to interface device */
1750 ret = regmap_write(wcd->if_regmap,
1751 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1752 payload);
1753
1754 if (ret < 0)
1755 goto err;
1756
1757 /* configure the slave port for water mark and enable*/
1758 ret = regmap_write(wcd->if_regmap,
1759 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1760 WCD9335_SLIM_WATER_MARK_VAL);
1761 if (ret < 0)
1762 goto err;
1763 } else {
1764 ret = regmap_write(wcd->if_regmap,
1765 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1766 payload & 0x00FF);
1767 if (ret < 0)
1768 goto err;
1769
1770 /* ports 8,9 */
1771 ret = regmap_write(wcd->if_regmap,
1772 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1773 (payload & 0xFF00)>>8);
1774 if (ret < 0)
1775 goto err;
1776
1777 /* configure the slave port for water mark and enable*/
1778 ret = regmap_write(wcd->if_regmap,
1779 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1780 WCD9335_SLIM_WATER_MARK_VAL);
1781
1782 if (ret < 0)
1783 goto err;
1784 }
1785 }
1786
1787 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1788
1789 return 0;
1790
1791 err:
1792 dev_err(wcd->dev, "Error Setting slim hw params\n");
1793 kfree(cfg->chs);
1794 cfg->chs = NULL;
1795
1796 return ret;
1797 }
1798
wcd9335_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1799 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1800 u8 rate_val, u32 rate)
1801 {
1802 struct snd_soc_component *comp = dai->component;
1803 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1804 u8 shift = 0, shift_val = 0, tx_mux_sel;
1805 struct wcd9335_slim_ch *ch;
1806 int tx_port, tx_port_reg;
1807 int decimator = -1;
1808
1809 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1810 tx_port = ch->port;
1811 if ((tx_port == 12) || (tx_port >= 14)) {
1812 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1813 tx_port, dai->id);
1814 return -EINVAL;
1815 }
1816 /* Find the SB TX MUX input - which decimator is connected */
1817 if (tx_port < 4) {
1818 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1819 shift = (tx_port << 1);
1820 shift_val = 0x03;
1821 } else if ((tx_port >= 4) && (tx_port < 8)) {
1822 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1823 shift = ((tx_port - 4) << 1);
1824 shift_val = 0x03;
1825 } else if ((tx_port >= 8) && (tx_port < 11)) {
1826 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1827 shift = ((tx_port - 8) << 1);
1828 shift_val = 0x03;
1829 } else if (tx_port == 11) {
1830 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1831 shift = 0;
1832 shift_val = 0x0F;
1833 } else if (tx_port == 13) {
1834 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1835 shift = 4;
1836 shift_val = 0x03;
1837 } else {
1838 return -EINVAL;
1839 }
1840
1841 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1842 (shift_val << shift);
1843
1844 tx_mux_sel = tx_mux_sel >> shift;
1845 if (tx_port <= 8) {
1846 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1847 decimator = tx_port;
1848 } else if (tx_port <= 10) {
1849 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1850 decimator = ((tx_port == 9) ? 7 : 6);
1851 } else if (tx_port == 11) {
1852 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1853 decimator = tx_mux_sel - 1;
1854 } else if (tx_port == 13) {
1855 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1856 decimator = 5;
1857 }
1858
1859 if (decimator >= 0) {
1860 snd_soc_component_update_bits(comp,
1861 WCD9335_CDC_TX_PATH_CTL(decimator),
1862 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1863 rate_val);
1864 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1865 /* Check if the TX Mux input is RX MIX TXn */
1866 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1867 tx_port, tx_port);
1868 } else {
1869 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1870 decimator);
1871 return -EINVAL;
1872 }
1873 }
1874
1875 return 0;
1876 }
1877
wcd9335_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1878 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1879 struct snd_pcm_hw_params *params,
1880 struct snd_soc_dai *dai)
1881 {
1882 struct wcd9335_codec *wcd;
1883 int ret, tx_fs_rate = 0;
1884
1885 wcd = snd_soc_component_get_drvdata(dai->component);
1886
1887 switch (substream->stream) {
1888 case SNDRV_PCM_STREAM_PLAYBACK:
1889 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1890 if (ret) {
1891 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1892 params_rate(params));
1893 return ret;
1894 }
1895 switch (params_width(params)) {
1896 case 16 ... 24:
1897 wcd->dai[dai->id].sconfig.bps = params_width(params);
1898 break;
1899 default:
1900 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1901 __func__, params_width(params));
1902 return -EINVAL;
1903 }
1904 break;
1905
1906 case SNDRV_PCM_STREAM_CAPTURE:
1907 switch (params_rate(params)) {
1908 case 8000:
1909 tx_fs_rate = 0;
1910 break;
1911 case 16000:
1912 tx_fs_rate = 1;
1913 break;
1914 case 32000:
1915 tx_fs_rate = 3;
1916 break;
1917 case 48000:
1918 tx_fs_rate = 4;
1919 break;
1920 case 96000:
1921 tx_fs_rate = 5;
1922 break;
1923 case 192000:
1924 tx_fs_rate = 6;
1925 break;
1926 case 384000:
1927 tx_fs_rate = 7;
1928 break;
1929 default:
1930 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1931 __func__, params_rate(params));
1932 return -EINVAL;
1933
1934 }
1935
1936 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1937 params_rate(params));
1938 if (ret < 0) {
1939 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1940 return ret;
1941 }
1942 switch (params_width(params)) {
1943 case 16 ... 32:
1944 wcd->dai[dai->id].sconfig.bps = params_width(params);
1945 break;
1946 default:
1947 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1948 __func__, params_width(params));
1949 return -EINVAL;
1950 }
1951 break;
1952 default:
1953 dev_err(wcd->dev, "Invalid stream type %d\n",
1954 substream->stream);
1955 return -EINVAL;
1956 }
1957
1958 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1959 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1960
1961 return 0;
1962 }
1963
wcd9335_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1964 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1965 struct snd_soc_dai *dai)
1966 {
1967 struct wcd_slim_codec_dai_data *dai_data;
1968 struct wcd9335_codec *wcd;
1969 struct slim_stream_config *cfg;
1970
1971 wcd = snd_soc_component_get_drvdata(dai->component);
1972
1973 dai_data = &wcd->dai[dai->id];
1974
1975 switch (cmd) {
1976 case SNDRV_PCM_TRIGGER_START:
1977 case SNDRV_PCM_TRIGGER_RESUME:
1978 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1979 cfg = &dai_data->sconfig;
1980 slim_stream_prepare(dai_data->sruntime, cfg);
1981 slim_stream_enable(dai_data->sruntime);
1982 break;
1983 case SNDRV_PCM_TRIGGER_STOP:
1984 case SNDRV_PCM_TRIGGER_SUSPEND:
1985 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1986 slim_stream_unprepare(dai_data->sruntime);
1987 slim_stream_disable(dai_data->sruntime);
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 return 0;
1994 }
1995
wcd9335_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,unsigned int * tx_slot,unsigned int rx_num,unsigned int * rx_slot)1996 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1997 unsigned int tx_num, unsigned int *tx_slot,
1998 unsigned int rx_num, unsigned int *rx_slot)
1999 {
2000 struct wcd9335_codec *wcd;
2001 int i;
2002
2003 wcd = snd_soc_component_get_drvdata(dai->component);
2004
2005 if (!tx_slot || !rx_slot) {
2006 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
2007 tx_slot, rx_slot);
2008 return -EINVAL;
2009 }
2010
2011 wcd->num_rx_port = rx_num;
2012 for (i = 0; i < rx_num; i++) {
2013 wcd->rx_chs[i].ch_num = rx_slot[i];
2014 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2015 }
2016
2017 wcd->num_tx_port = tx_num;
2018 for (i = 0; i < tx_num; i++) {
2019 wcd->tx_chs[i].ch_num = tx_slot[i];
2020 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2021 }
2022
2023 return 0;
2024 }
2025
wcd9335_get_channel_map(struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)2026 static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
2027 unsigned int *tx_num, unsigned int *tx_slot,
2028 unsigned int *rx_num, unsigned int *rx_slot)
2029 {
2030 struct wcd9335_slim_ch *ch;
2031 struct wcd9335_codec *wcd;
2032 int i = 0;
2033
2034 wcd = snd_soc_component_get_drvdata(dai->component);
2035
2036 switch (dai->id) {
2037 case AIF1_PB:
2038 case AIF2_PB:
2039 case AIF3_PB:
2040 case AIF4_PB:
2041 if (!rx_slot || !rx_num) {
2042 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2043 rx_slot, rx_num);
2044 return -EINVAL;
2045 }
2046
2047 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2048 rx_slot[i++] = ch->ch_num;
2049
2050 *rx_num = i;
2051 break;
2052 case AIF1_CAP:
2053 case AIF2_CAP:
2054 case AIF3_CAP:
2055 if (!tx_slot || !tx_num) {
2056 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2057 tx_slot, tx_num);
2058 return -EINVAL;
2059 }
2060 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2061 tx_slot[i++] = ch->ch_num;
2062
2063 *tx_num = i;
2064 break;
2065 default:
2066 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2067 break;
2068 }
2069
2070 return 0;
2071 }
2072
2073 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2074 .hw_params = wcd9335_hw_params,
2075 .trigger = wcd9335_trigger,
2076 .set_channel_map = wcd9335_set_channel_map,
2077 .get_channel_map = wcd9335_get_channel_map,
2078 };
2079
2080 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2081 [0] = {
2082 .name = "wcd9335_rx1",
2083 .id = AIF1_PB,
2084 .playback = {
2085 .stream_name = "AIF1 Playback",
2086 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2087 SNDRV_PCM_RATE_384000,
2088 .formats = WCD9335_FORMATS_S16_S24_LE,
2089 .rate_max = 384000,
2090 .rate_min = 8000,
2091 .channels_min = 1,
2092 .channels_max = 2,
2093 },
2094 .ops = &wcd9335_dai_ops,
2095 },
2096 [1] = {
2097 .name = "wcd9335_tx1",
2098 .id = AIF1_CAP,
2099 .capture = {
2100 .stream_name = "AIF1 Capture",
2101 .rates = WCD9335_RATES_MASK,
2102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2103 .rate_min = 8000,
2104 .rate_max = 192000,
2105 .channels_min = 1,
2106 .channels_max = 4,
2107 },
2108 .ops = &wcd9335_dai_ops,
2109 },
2110 [2] = {
2111 .name = "wcd9335_rx2",
2112 .id = AIF2_PB,
2113 .playback = {
2114 .stream_name = "AIF2 Playback",
2115 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2116 SNDRV_PCM_RATE_384000,
2117 .formats = WCD9335_FORMATS_S16_S24_LE,
2118 .rate_min = 8000,
2119 .rate_max = 384000,
2120 .channels_min = 1,
2121 .channels_max = 2,
2122 },
2123 .ops = &wcd9335_dai_ops,
2124 },
2125 [3] = {
2126 .name = "wcd9335_tx2",
2127 .id = AIF2_CAP,
2128 .capture = {
2129 .stream_name = "AIF2 Capture",
2130 .rates = WCD9335_RATES_MASK,
2131 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2132 .rate_min = 8000,
2133 .rate_max = 192000,
2134 .channels_min = 1,
2135 .channels_max = 4,
2136 },
2137 .ops = &wcd9335_dai_ops,
2138 },
2139 [4] = {
2140 .name = "wcd9335_rx3",
2141 .id = AIF3_PB,
2142 .playback = {
2143 .stream_name = "AIF3 Playback",
2144 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2145 SNDRV_PCM_RATE_384000,
2146 .formats = WCD9335_FORMATS_S16_S24_LE,
2147 .rate_min = 8000,
2148 .rate_max = 384000,
2149 .channels_min = 1,
2150 .channels_max = 2,
2151 },
2152 .ops = &wcd9335_dai_ops,
2153 },
2154 [5] = {
2155 .name = "wcd9335_tx3",
2156 .id = AIF3_CAP,
2157 .capture = {
2158 .stream_name = "AIF3 Capture",
2159 .rates = WCD9335_RATES_MASK,
2160 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2161 .rate_min = 8000,
2162 .rate_max = 192000,
2163 .channels_min = 1,
2164 .channels_max = 4,
2165 },
2166 .ops = &wcd9335_dai_ops,
2167 },
2168 [6] = {
2169 .name = "wcd9335_rx4",
2170 .id = AIF4_PB,
2171 .playback = {
2172 .stream_name = "AIF4 Playback",
2173 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2174 SNDRV_PCM_RATE_384000,
2175 .formats = WCD9335_FORMATS_S16_S24_LE,
2176 .rate_min = 8000,
2177 .rate_max = 384000,
2178 .channels_min = 1,
2179 .channels_max = 2,
2180 },
2181 .ops = &wcd9335_dai_ops,
2182 },
2183 };
2184
wcd9335_get_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2185 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2186 struct snd_ctl_elem_value *ucontrol)
2187 {
2188
2189 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2190 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2191 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2192
2193 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2194 return 0;
2195 }
2196
wcd9335_set_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2197 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2198 struct snd_ctl_elem_value *ucontrol)
2199 {
2200 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2201 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2202 int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2203 int value = ucontrol->value.integer.value[0];
2204 int sel;
2205
2206 wcd->comp_enabled[comp] = value;
2207 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2208 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2209
2210 /* Any specific register configuration for compander */
2211 switch (comp) {
2212 case COMPANDER_1:
2213 /* Set Gain Source Select based on compander enable/disable */
2214 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2215 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2216 break;
2217 case COMPANDER_2:
2218 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2219 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2220 break;
2221 case COMPANDER_5:
2222 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2223 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2224 break;
2225 case COMPANDER_6:
2226 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2227 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2228 break;
2229 default:
2230 break;
2231 }
2232
2233 return 0;
2234 }
2235
wcd9335_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2236 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2237 struct snd_ctl_elem_value *ucontrol)
2238 {
2239 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2241
2242 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2243
2244 return 0;
2245 }
2246
wcd9335_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2247 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2248 struct snd_ctl_elem_value *ucontrol)
2249 {
2250 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2251 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2252 u32 mode_val;
2253
2254 mode_val = ucontrol->value.enumerated.item[0];
2255
2256 if (mode_val == 0) {
2257 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2258 mode_val = CLS_H_HIFI;
2259 }
2260 wcd->hph_mode = mode_val;
2261
2262 return 0;
2263 }
2264
2265 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2266 /* -84dB min - 40dB max */
2267 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2268 -84, 40, digital_gain),
2269 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2270 -84, 40, digital_gain),
2271 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2272 -84, 40, digital_gain),
2273 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2274 -84, 40, digital_gain),
2275 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2276 -84, 40, digital_gain),
2277 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2278 -84, 40, digital_gain),
2279 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2280 -84, 40, digital_gain),
2281 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2282 -84, 40, digital_gain),
2283 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2284 -84, 40, digital_gain),
2285 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2286 -84, 40, digital_gain),
2287 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2288 -84, 40, digital_gain),
2289 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2290 -84, 40, digital_gain),
2291 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2292 -84, 40, digital_gain),
2293 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2294 -84, 40, digital_gain),
2295 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2296 -84, 40, digital_gain),
2297 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2298 -84, 40, digital_gain),
2299 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2300 -84, 40, digital_gain),
2301 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2302 -84, 40, digital_gain),
2303 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2304 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2305 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2306 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2307 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2308 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2309 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2310 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2311 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2312 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2313 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2314 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2315 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2316 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2317 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2318 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2319 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2320 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2321 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2322 wcd9335_get_compander, wcd9335_set_compander),
2323 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2324 wcd9335_get_compander, wcd9335_set_compander),
2325 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2326 wcd9335_get_compander, wcd9335_set_compander),
2327 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2328 wcd9335_get_compander, wcd9335_set_compander),
2329 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2330 wcd9335_get_compander, wcd9335_set_compander),
2331 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2332 wcd9335_get_compander, wcd9335_set_compander),
2333 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2334 wcd9335_get_compander, wcd9335_set_compander),
2335 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2336 wcd9335_get_compander, wcd9335_set_compander),
2337 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2338 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2339
2340 /* Gain Controls */
2341 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2342 ear_pa_gain),
2343 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2344 line_gain),
2345 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2346 line_gain),
2347 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2348 3, 16, 1, line_gain),
2349 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2350 3, 16, 1, line_gain),
2351 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2352 line_gain),
2353 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2354 line_gain),
2355
2356 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2357 analog_gain),
2358 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2359 analog_gain),
2360 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2361 analog_gain),
2362 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2363 analog_gain),
2364 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2365 analog_gain),
2366 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2367 analog_gain),
2368
2369 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2370 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2371 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2372 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2373 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2374 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2375 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2376 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2377 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2378 };
2379
2380 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2381 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2382 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2383 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2384 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2385 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2386 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2387 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2388 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2389
2390 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2391 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2392 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2393 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2394 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2395 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2396 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2397 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2398
2399 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2400 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2401 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2402 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2403 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2404 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2405 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2406 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2407
2408 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2409 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2410 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2411 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2412 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2413 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2414 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2415 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2416
2417 {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2418 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2419 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2420 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2421 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2422 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2423 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2424 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2425
2426 WCD9335_INTERPOLATOR_PATH(0),
2427 WCD9335_INTERPOLATOR_PATH(1),
2428 WCD9335_INTERPOLATOR_PATH(2),
2429 WCD9335_INTERPOLATOR_PATH(3),
2430 WCD9335_INTERPOLATOR_PATH(4),
2431 WCD9335_INTERPOLATOR_PATH(5),
2432 WCD9335_INTERPOLATOR_PATH(6),
2433 WCD9335_INTERPOLATOR_PATH(7),
2434 WCD9335_INTERPOLATOR_PATH(8),
2435
2436 /* EAR PA */
2437 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2438 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2439 {"RX INT0 DAC", NULL, "RX_BIAS"},
2440 {"EAR PA", NULL, "RX INT0 DAC"},
2441 {"EAR", NULL, "EAR PA"},
2442
2443 /* HPHL */
2444 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2445 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2446 {"RX INT1 DAC", NULL, "RX_BIAS"},
2447 {"HPHL PA", NULL, "RX INT1 DAC"},
2448 {"HPHL", NULL, "HPHL PA"},
2449
2450 /* HPHR */
2451 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2452 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2453 {"RX INT2 DAC", NULL, "RX_BIAS"},
2454 {"HPHR PA", NULL, "RX INT2 DAC"},
2455 {"HPHR", NULL, "HPHR PA"},
2456
2457 /* LINEOUT1 */
2458 {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2459 {"RX INT3 DAC", NULL, "RX_BIAS"},
2460 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2461 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2462
2463 /* LINEOUT2 */
2464 {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2465 {"RX INT4 DAC", NULL, "RX_BIAS"},
2466 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2467 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2468
2469 /* LINEOUT3 */
2470 {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2471 {"RX INT5 DAC", NULL, "RX_BIAS"},
2472 {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2473 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2474
2475 /* LINEOUT4 */
2476 {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2477 {"RX INT6 DAC", NULL, "RX_BIAS"},
2478 {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2479 {"LINEOUT4", NULL, "LINEOUT4 PA"},
2480
2481 /* SLIMBUS Connections */
2482 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2483 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2484 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2485
2486 /* ADC Mux */
2487 WCD9335_ADC_MUX_PATH(0),
2488 WCD9335_ADC_MUX_PATH(1),
2489 WCD9335_ADC_MUX_PATH(2),
2490 WCD9335_ADC_MUX_PATH(3),
2491 WCD9335_ADC_MUX_PATH(4),
2492 WCD9335_ADC_MUX_PATH(5),
2493 WCD9335_ADC_MUX_PATH(6),
2494 WCD9335_ADC_MUX_PATH(7),
2495 WCD9335_ADC_MUX_PATH(8),
2496
2497 /* ADC Connections */
2498 {"ADC1", NULL, "AMIC1"},
2499 {"ADC2", NULL, "AMIC2"},
2500 {"ADC3", NULL, "AMIC3"},
2501 {"ADC4", NULL, "AMIC4"},
2502 {"ADC5", NULL, "AMIC5"},
2503 {"ADC6", NULL, "AMIC6"},
2504 };
2505
wcd9335_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2506 static int wcd9335_micbias_control(struct snd_soc_component *component,
2507 int micb_num, int req, bool is_dapm)
2508 {
2509 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2510 int micb_index = micb_num - 1;
2511 u16 micb_reg;
2512
2513 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2514 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2515 micb_index);
2516 return -EINVAL;
2517 }
2518
2519 switch (micb_num) {
2520 case MIC_BIAS_1:
2521 micb_reg = WCD9335_ANA_MICB1;
2522 break;
2523 case MIC_BIAS_2:
2524 micb_reg = WCD9335_ANA_MICB2;
2525 break;
2526 case MIC_BIAS_3:
2527 micb_reg = WCD9335_ANA_MICB3;
2528 break;
2529 case MIC_BIAS_4:
2530 micb_reg = WCD9335_ANA_MICB4;
2531 break;
2532 default:
2533 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2534 __func__, micb_num);
2535 return -EINVAL;
2536 }
2537
2538 switch (req) {
2539 case MICB_PULLUP_ENABLE:
2540 wcd->pullup_ref[micb_index]++;
2541 if ((wcd->pullup_ref[micb_index] == 1) &&
2542 (wcd->micb_ref[micb_index] == 0))
2543 snd_soc_component_update_bits(component, micb_reg,
2544 0xC0, 0x80);
2545 break;
2546 case MICB_PULLUP_DISABLE:
2547 wcd->pullup_ref[micb_index]--;
2548 if ((wcd->pullup_ref[micb_index] == 0) &&
2549 (wcd->micb_ref[micb_index] == 0))
2550 snd_soc_component_update_bits(component, micb_reg,
2551 0xC0, 0x00);
2552 break;
2553 case MICB_ENABLE:
2554 wcd->micb_ref[micb_index]++;
2555 if (wcd->micb_ref[micb_index] == 1)
2556 snd_soc_component_update_bits(component, micb_reg,
2557 0xC0, 0x40);
2558 break;
2559 case MICB_DISABLE:
2560 wcd->micb_ref[micb_index]--;
2561 if ((wcd->micb_ref[micb_index] == 0) &&
2562 (wcd->pullup_ref[micb_index] > 0))
2563 snd_soc_component_update_bits(component, micb_reg,
2564 0xC0, 0x80);
2565 else if ((wcd->micb_ref[micb_index] == 0) &&
2566 (wcd->pullup_ref[micb_index] == 0)) {
2567 snd_soc_component_update_bits(component, micb_reg,
2568 0xC0, 0x00);
2569 }
2570 break;
2571 }
2572
2573 return 0;
2574 }
2575
__wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)2576 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2577 int event)
2578 {
2579 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2580 int micb_num;
2581
2582 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2583 micb_num = MIC_BIAS_1;
2584 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2585 micb_num = MIC_BIAS_2;
2586 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2587 micb_num = MIC_BIAS_3;
2588 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2589 micb_num = MIC_BIAS_4;
2590 else
2591 return -EINVAL;
2592
2593 switch (event) {
2594 case SND_SOC_DAPM_PRE_PMU:
2595 /*
2596 * MIC BIAS can also be requested by MBHC,
2597 * so use ref count to handle micbias pullup
2598 * and enable requests
2599 */
2600 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2601 break;
2602 case SND_SOC_DAPM_POST_PMU:
2603 /* wait for cnp time */
2604 usleep_range(1000, 1100);
2605 break;
2606 case SND_SOC_DAPM_POST_PMD:
2607 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2608 break;
2609 }
2610
2611 return 0;
2612 }
2613
wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2614 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2615 struct snd_kcontrol *kc, int event)
2616 {
2617 return __wcd9335_codec_enable_micbias(w, event);
2618 }
2619
wcd9335_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)2620 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2621 u16 amic_reg, bool set)
2622 {
2623 u8 mask = 0x20;
2624 u8 val;
2625
2626 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2627 amic_reg == WCD9335_ANA_AMIC5)
2628 mask = 0x40;
2629
2630 val = set ? mask : 0x00;
2631
2632 switch (amic_reg) {
2633 case WCD9335_ANA_AMIC1:
2634 case WCD9335_ANA_AMIC2:
2635 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2636 val);
2637 break;
2638 case WCD9335_ANA_AMIC3:
2639 case WCD9335_ANA_AMIC4:
2640 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2641 val);
2642 break;
2643 case WCD9335_ANA_AMIC5:
2644 case WCD9335_ANA_AMIC6:
2645 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2646 val);
2647 break;
2648 default:
2649 dev_err(comp->dev, "%s: invalid amic: %d\n",
2650 __func__, amic_reg);
2651 break;
2652 }
2653 }
2654
wcd9335_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2655 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2656 struct snd_kcontrol *kc, int event)
2657 {
2658 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2659
2660 switch (event) {
2661 case SND_SOC_DAPM_PRE_PMU:
2662 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2663 break;
2664 default:
2665 break;
2666 }
2667
2668 return 0;
2669 }
2670
wcd9335_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)2671 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2672 int adc_mux_n)
2673 {
2674 int mux_sel, reg, mreg;
2675
2676 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2677 adc_mux_n == WCD9335_INVALID_ADC_MUX)
2678 return 0;
2679
2680 /* Check whether adc mux input is AMIC or DMIC */
2681 if (adc_mux_n < 4) {
2682 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2683 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2684 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2685 } else {
2686 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2687 mreg = reg;
2688 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2689 }
2690
2691 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2692 return 0;
2693
2694 return snd_soc_component_read(comp, mreg) & 0x07;
2695 }
2696
wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)2697 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2698 int amic)
2699 {
2700 u16 pwr_level_reg = 0;
2701
2702 switch (amic) {
2703 case 1:
2704 case 2:
2705 pwr_level_reg = WCD9335_ANA_AMIC1;
2706 break;
2707
2708 case 3:
2709 case 4:
2710 pwr_level_reg = WCD9335_ANA_AMIC3;
2711 break;
2712
2713 case 5:
2714 case 6:
2715 pwr_level_reg = WCD9335_ANA_AMIC5;
2716 break;
2717 default:
2718 dev_err(comp->dev, "invalid amic: %d\n", amic);
2719 break;
2720 }
2721
2722 return pwr_level_reg;
2723 }
2724
wcd9335_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2725 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2726 struct snd_kcontrol *kc, int event)
2727 {
2728 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2729 unsigned int decimator;
2730 char *dec_adc_mux_name = NULL;
2731 char *widget_name = NULL;
2732 char *wname;
2733 int ret = 0, amic_n;
2734 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2735 u16 tx_gain_ctl_reg;
2736 char *dec;
2737 u8 hpf_coff_freq;
2738
2739 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
2740 if (!widget_name)
2741 return -ENOMEM;
2742
2743 wname = widget_name;
2744 dec_adc_mux_name = strsep(&widget_name, " ");
2745 if (!dec_adc_mux_name) {
2746 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2747 __func__, w->name);
2748 ret = -EINVAL;
2749 goto out;
2750 }
2751 dec_adc_mux_name = widget_name;
2752
2753 dec = strpbrk(dec_adc_mux_name, "012345678");
2754 if (!dec) {
2755 dev_err(comp->dev, "%s: decimator index not found\n",
2756 __func__);
2757 ret = -EINVAL;
2758 goto out;
2759 }
2760
2761 ret = kstrtouint(dec, 10, &decimator);
2762 if (ret < 0) {
2763 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2764 __func__, wname);
2765 ret = -EINVAL;
2766 goto out;
2767 }
2768
2769 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2770 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2771 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2772 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2773
2774 switch (event) {
2775 case SND_SOC_DAPM_PRE_PMU:
2776 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2777 if (amic_n)
2778 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2779 amic_n);
2780
2781 if (pwr_level_reg) {
2782 switch ((snd_soc_component_read(comp, pwr_level_reg) &
2783 WCD9335_AMIC_PWR_LVL_MASK) >>
2784 WCD9335_AMIC_PWR_LVL_SHIFT) {
2785 case WCD9335_AMIC_PWR_LEVEL_LP:
2786 snd_soc_component_update_bits(comp, dec_cfg_reg,
2787 WCD9335_DEC_PWR_LVL_MASK,
2788 WCD9335_DEC_PWR_LVL_LP);
2789 break;
2790
2791 case WCD9335_AMIC_PWR_LEVEL_HP:
2792 snd_soc_component_update_bits(comp, dec_cfg_reg,
2793 WCD9335_DEC_PWR_LVL_MASK,
2794 WCD9335_DEC_PWR_LVL_HP);
2795 break;
2796 case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2797 default:
2798 snd_soc_component_update_bits(comp, dec_cfg_reg,
2799 WCD9335_DEC_PWR_LVL_MASK,
2800 WCD9335_DEC_PWR_LVL_DF);
2801 break;
2802 }
2803 }
2804 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2805 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2806
2807 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2808 snd_soc_component_update_bits(comp, dec_cfg_reg,
2809 TX_HPF_CUT_OFF_FREQ_MASK,
2810 CF_MIN_3DB_150HZ << 5);
2811 /* Enable TX PGA Mute */
2812 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2813 0x10, 0x10);
2814 /* Enable APC */
2815 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2816 break;
2817 case SND_SOC_DAPM_POST_PMU:
2818 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2819
2820 if (decimator == 0) {
2821 snd_soc_component_write(comp,
2822 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2823 snd_soc_component_write(comp,
2824 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2825 snd_soc_component_write(comp,
2826 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2827 snd_soc_component_write(comp,
2828 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2829 }
2830
2831 snd_soc_component_update_bits(comp, hpf_gate_reg,
2832 0x01, 0x01);
2833 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2834 0x10, 0x00);
2835 snd_soc_component_write(comp, tx_gain_ctl_reg,
2836 snd_soc_component_read(comp, tx_gain_ctl_reg));
2837 break;
2838 case SND_SOC_DAPM_PRE_PMD:
2839 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2840 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2841 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2842 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2843 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2844 snd_soc_component_update_bits(comp, dec_cfg_reg,
2845 TX_HPF_CUT_OFF_FREQ_MASK,
2846 hpf_coff_freq << 5);
2847 }
2848 break;
2849 case SND_SOC_DAPM_POST_PMD:
2850 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2851 break;
2852 }
2853 out:
2854 kfree(wname);
2855 return ret;
2856 }
2857
wcd9335_get_dmic_clk_val(struct snd_soc_component * component,u32 mclk_rate,u32 dmic_clk_rate)2858 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2859 u32 mclk_rate, u32 dmic_clk_rate)
2860 {
2861 u32 div_factor;
2862 u8 dmic_ctl_val;
2863
2864 dev_err(component->dev,
2865 "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
2866 __func__, mclk_rate, dmic_clk_rate);
2867
2868 /* Default value to return in case of error */
2869 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2870 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2871 else
2872 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2873
2874 if (dmic_clk_rate == 0) {
2875 dev_err(component->dev,
2876 "%s: dmic_sample_rate cannot be 0\n",
2877 __func__);
2878 goto done;
2879 }
2880
2881 div_factor = mclk_rate / dmic_clk_rate;
2882 switch (div_factor) {
2883 case 2:
2884 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2885 break;
2886 case 3:
2887 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2888 break;
2889 case 4:
2890 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
2891 break;
2892 case 6:
2893 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
2894 break;
2895 case 8:
2896 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
2897 break;
2898 case 16:
2899 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
2900 break;
2901 default:
2902 dev_err(component->dev,
2903 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
2904 __func__, div_factor, mclk_rate, dmic_clk_rate);
2905 break;
2906 }
2907
2908 done:
2909 return dmic_ctl_val;
2910 }
2911
wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2912 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2913 struct snd_kcontrol *kc, int event)
2914 {
2915 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2916 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2917 u8 dmic_clk_en = 0x01;
2918 u16 dmic_clk_reg;
2919 s32 *dmic_clk_cnt;
2920 u8 dmic_rate_val, dmic_rate_shift = 1;
2921 unsigned int dmic;
2922 int ret;
2923 char *wname;
2924
2925 wname = strpbrk(w->name, "012345");
2926 if (!wname) {
2927 dev_err(comp->dev, "%s: widget not found\n", __func__);
2928 return -EINVAL;
2929 }
2930
2931 ret = kstrtouint(wname, 10, &dmic);
2932 if (ret < 0) {
2933 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2934 __func__);
2935 return -EINVAL;
2936 }
2937
2938 switch (dmic) {
2939 case 0:
2940 case 1:
2941 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2942 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2943 break;
2944 case 2:
2945 case 3:
2946 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2947 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2948 break;
2949 case 4:
2950 case 5:
2951 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2952 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2953 break;
2954 default:
2955 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2956 __func__);
2957 return -EINVAL;
2958 }
2959
2960 switch (event) {
2961 case SND_SOC_DAPM_PRE_PMU:
2962 dmic_rate_val =
2963 wcd9335_get_dmic_clk_val(comp,
2964 wcd->mclk_rate,
2965 wcd->dmic_sample_rate);
2966
2967 (*dmic_clk_cnt)++;
2968 if (*dmic_clk_cnt == 1) {
2969 snd_soc_component_update_bits(comp, dmic_clk_reg,
2970 0x07 << dmic_rate_shift,
2971 dmic_rate_val << dmic_rate_shift);
2972 snd_soc_component_update_bits(comp, dmic_clk_reg,
2973 dmic_clk_en, dmic_clk_en);
2974 }
2975
2976 break;
2977 case SND_SOC_DAPM_POST_PMD:
2978 dmic_rate_val =
2979 wcd9335_get_dmic_clk_val(comp,
2980 wcd->mclk_rate,
2981 wcd->mad_dmic_sample_rate);
2982 (*dmic_clk_cnt)--;
2983 if (*dmic_clk_cnt == 0) {
2984 snd_soc_component_update_bits(comp, dmic_clk_reg,
2985 dmic_clk_en, 0);
2986 snd_soc_component_update_bits(comp, dmic_clk_reg,
2987 0x07 << dmic_rate_shift,
2988 dmic_rate_val << dmic_rate_shift);
2989 }
2990 break;
2991 }
2992
2993 return 0;
2994 }
2995
wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)2996 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2997 struct snd_soc_component *component)
2998 {
2999 int port_num = 0;
3000 unsigned short reg = 0;
3001 unsigned int val = 0;
3002 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3003 struct wcd9335_slim_ch *ch;
3004
3005 list_for_each_entry(ch, &dai->slim_ch_list, list) {
3006 if (ch->port >= WCD9335_RX_START) {
3007 port_num = ch->port - WCD9335_RX_START;
3008 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3009 } else {
3010 port_num = ch->port;
3011 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3012 }
3013
3014 regmap_read(wcd->if_regmap, reg, &val);
3015 if (!(val & BIT(port_num % 8)))
3016 regmap_write(wcd->if_regmap, reg,
3017 val | BIT(port_num % 8));
3018 }
3019 }
3020
wcd9335_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3021 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
3022 struct snd_kcontrol *kc,
3023 int event)
3024 {
3025 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3026 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
3027 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3028
3029 switch (event) {
3030 case SND_SOC_DAPM_POST_PMU:
3031 wcd9335_codec_enable_int_port(dai, comp);
3032 break;
3033 case SND_SOC_DAPM_POST_PMD:
3034 kfree(dai->sconfig.chs);
3035
3036 break;
3037 }
3038
3039 return 0;
3040 }
3041
wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3042 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3043 struct snd_kcontrol *kc, int event)
3044 {
3045 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3046 u16 gain_reg;
3047 int offset_val = 0;
3048 int val = 0;
3049
3050 switch (w->reg) {
3051 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3052 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
3053 break;
3054 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3055 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
3056 break;
3057 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3058 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
3059 break;
3060 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3061 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
3062 break;
3063 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3064 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3065 break;
3066 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3067 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3068 break;
3069 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3070 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3071 break;
3072 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3073 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3074 break;
3075 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3076 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3077 break;
3078 default:
3079 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3080 __func__, w->name);
3081 return 0;
3082 }
3083
3084 switch (event) {
3085 case SND_SOC_DAPM_POST_PMU:
3086 val = snd_soc_component_read(comp, gain_reg);
3087 val += offset_val;
3088 snd_soc_component_write(comp, gain_reg, val);
3089 break;
3090 case SND_SOC_DAPM_POST_PMD:
3091 break;
3092 }
3093
3094 return 0;
3095 }
3096
wcd9335_interp_get_primary_reg(u16 reg,u16 * ind)3097 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3098 {
3099 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3100
3101 switch (reg) {
3102 case WCD9335_CDC_RX0_RX_PATH_CTL:
3103 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3104 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3105 *ind = 0;
3106 break;
3107 case WCD9335_CDC_RX1_RX_PATH_CTL:
3108 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3109 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3110 *ind = 1;
3111 break;
3112 case WCD9335_CDC_RX2_RX_PATH_CTL:
3113 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3114 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3115 *ind = 2;
3116 break;
3117 case WCD9335_CDC_RX3_RX_PATH_CTL:
3118 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3119 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3120 *ind = 3;
3121 break;
3122 case WCD9335_CDC_RX4_RX_PATH_CTL:
3123 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3124 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3125 *ind = 4;
3126 break;
3127 case WCD9335_CDC_RX5_RX_PATH_CTL:
3128 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3129 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3130 *ind = 5;
3131 break;
3132 case WCD9335_CDC_RX6_RX_PATH_CTL:
3133 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3134 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3135 *ind = 6;
3136 break;
3137 case WCD9335_CDC_RX7_RX_PATH_CTL:
3138 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3139 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3140 *ind = 7;
3141 break;
3142 case WCD9335_CDC_RX8_RX_PATH_CTL:
3143 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3144 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3145 *ind = 8;
3146 break;
3147 }
3148
3149 return prim_int_reg;
3150 }
3151
wcd9335_codec_hd2_control(struct snd_soc_component * component,u16 prim_int_reg,int event)3152 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3153 u16 prim_int_reg, int event)
3154 {
3155 u16 hd2_scale_reg;
3156 u16 hd2_enable_reg = 0;
3157
3158 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3159 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3160 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3161 }
3162 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3163 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3164 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3165 }
3166
3167 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3168 snd_soc_component_update_bits(component, hd2_scale_reg,
3169 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3170 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3171 snd_soc_component_update_bits(component, hd2_scale_reg,
3172 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3173 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3174 snd_soc_component_update_bits(component, hd2_enable_reg,
3175 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3176 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3177 }
3178
3179 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3180 snd_soc_component_update_bits(component, hd2_enable_reg,
3181 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3182 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3183 snd_soc_component_update_bits(component, hd2_scale_reg,
3184 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3185 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3186 snd_soc_component_update_bits(component, hd2_scale_reg,
3187 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3188 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3189 }
3190 }
3191
wcd9335_codec_enable_prim_interpolator(struct snd_soc_component * comp,u16 reg,int event)3192 static int wcd9335_codec_enable_prim_interpolator(
3193 struct snd_soc_component *comp,
3194 u16 reg, int event)
3195 {
3196 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3197 u16 ind = 0;
3198 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3199
3200 switch (event) {
3201 case SND_SOC_DAPM_PRE_PMU:
3202 wcd->prim_int_users[ind]++;
3203 if (wcd->prim_int_users[ind] == 1) {
3204 snd_soc_component_update_bits(comp, prim_int_reg,
3205 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3206 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3207 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3208 snd_soc_component_update_bits(comp, prim_int_reg,
3209 WCD9335_CDC_RX_CLK_EN_MASK,
3210 WCD9335_CDC_RX_CLK_ENABLE);
3211 }
3212
3213 if ((reg != prim_int_reg) &&
3214 ((snd_soc_component_read(comp, prim_int_reg)) &
3215 WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3216 snd_soc_component_update_bits(comp, reg,
3217 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3218 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3219 break;
3220 case SND_SOC_DAPM_POST_PMD:
3221 wcd->prim_int_users[ind]--;
3222 if (wcd->prim_int_users[ind] == 0) {
3223 snd_soc_component_update_bits(comp, prim_int_reg,
3224 WCD9335_CDC_RX_CLK_EN_MASK,
3225 WCD9335_CDC_RX_CLK_DISABLE);
3226 snd_soc_component_update_bits(comp, prim_int_reg,
3227 WCD9335_CDC_RX_RESET_MASK,
3228 WCD9335_CDC_RX_RESET_ENABLE);
3229 snd_soc_component_update_bits(comp, prim_int_reg,
3230 WCD9335_CDC_RX_RESET_MASK,
3231 WCD9335_CDC_RX_RESET_DISABLE);
3232 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3233 }
3234 break;
3235 }
3236
3237 return 0;
3238 }
3239
wcd9335_config_compander(struct snd_soc_component * component,int interp_n,int event)3240 static int wcd9335_config_compander(struct snd_soc_component *component,
3241 int interp_n, int event)
3242 {
3243 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3244 int comp;
3245 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3246
3247 /* EAR does not have compander */
3248 if (!interp_n)
3249 return 0;
3250
3251 comp = interp_n - 1;
3252 if (!wcd->comp_enabled[comp])
3253 return 0;
3254
3255 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3256 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3257
3258 if (SND_SOC_DAPM_EVENT_ON(event)) {
3259 /* Enable Compander Clock */
3260 snd_soc_component_update_bits(component, comp_ctl0_reg,
3261 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3262 WCD9335_CDC_COMPANDER_CLK_ENABLE);
3263 /* Reset comander */
3264 snd_soc_component_update_bits(component, comp_ctl0_reg,
3265 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3266 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3267 snd_soc_component_update_bits(component, comp_ctl0_reg,
3268 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3269 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3270 /* Enables DRE in this path */
3271 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3272 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3273 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3274 }
3275
3276 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3277 snd_soc_component_update_bits(component, comp_ctl0_reg,
3278 WCD9335_CDC_COMPANDER_HALT_MASK,
3279 WCD9335_CDC_COMPANDER_HALT);
3280 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3281 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3282 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3283
3284 snd_soc_component_update_bits(component, comp_ctl0_reg,
3285 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3286 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3287 snd_soc_component_update_bits(component, comp_ctl0_reg,
3288 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3289 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3290 snd_soc_component_update_bits(component, comp_ctl0_reg,
3291 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3292 WCD9335_CDC_COMPANDER_CLK_DISABLE);
3293 snd_soc_component_update_bits(component, comp_ctl0_reg,
3294 WCD9335_CDC_COMPANDER_HALT_MASK,
3295 WCD9335_CDC_COMPANDER_NOHALT);
3296 }
3297
3298 return 0;
3299 }
3300
wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3301 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3302 struct snd_kcontrol *kc, int event)
3303 {
3304 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3305 u16 gain_reg;
3306 u16 reg;
3307 int val;
3308 int offset_val = 0;
3309
3310 if (!(strcmp(w->name, "RX INT0 INTERP"))) {
3311 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3312 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3313 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
3314 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3315 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3316 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
3317 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3318 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3319 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
3320 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3321 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3322 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
3323 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3324 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3325 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
3326 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3327 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3328 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
3329 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3330 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3331 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
3332 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3333 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3334 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
3335 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3336 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3337 } else {
3338 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3339 __func__);
3340 return -EINVAL;
3341 }
3342
3343 switch (event) {
3344 case SND_SOC_DAPM_PRE_PMU:
3345 /* Reset if needed */
3346 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3347 break;
3348 case SND_SOC_DAPM_POST_PMU:
3349 wcd9335_config_compander(comp, w->shift, event);
3350 val = snd_soc_component_read(comp, gain_reg);
3351 val += offset_val;
3352 snd_soc_component_write(comp, gain_reg, val);
3353 break;
3354 case SND_SOC_DAPM_POST_PMD:
3355 wcd9335_config_compander(comp, w->shift, event);
3356 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3357 break;
3358 }
3359
3360 return 0;
3361 }
3362
wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component * component,u8 gain)3363 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3364 u8 gain)
3365 {
3366 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3367 u8 hph_l_en, hph_r_en;
3368 u8 l_val, r_val;
3369 u8 hph_pa_status;
3370 bool is_hphl_pa, is_hphr_pa;
3371
3372 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3373 is_hphl_pa = hph_pa_status >> 7;
3374 is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3375
3376 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3377 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3378
3379 l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3380 r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3381
3382 /*
3383 * Set HPH_L & HPH_R gain source selection to REGISTER
3384 * for better click and pop only if corresponding PAs are
3385 * not enabled. Also cache the values of the HPHL/R
3386 * PA gains to be applied after PAs are enabled
3387 */
3388 if ((l_val != hph_l_en) && !is_hphl_pa) {
3389 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3390 wcd->hph_l_gain = hph_l_en & 0x1F;
3391 }
3392
3393 if ((r_val != hph_r_en) && !is_hphr_pa) {
3394 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3395 wcd->hph_r_gain = hph_r_en & 0x1F;
3396 }
3397 }
3398
wcd9335_codec_hph_lohifi_config(struct snd_soc_component * comp,int event)3399 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3400 int event)
3401 {
3402 if (SND_SOC_DAPM_EVENT_ON(event)) {
3403 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3404 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3405 0x06);
3406 snd_soc_component_update_bits(comp,
3407 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3408 0xF0, 0x40);
3409 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3410 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3411 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3412 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3413 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3414 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3415 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3416 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3417 0x0C);
3418 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3419 }
3420
3421 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3422 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3423 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3424 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3425 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3426 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3427 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3428 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3429 0x8A);
3430 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3431 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3432 0x0A);
3433 }
3434 }
3435
wcd9335_codec_hph_lp_config(struct snd_soc_component * comp,int event)3436 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3437 int event)
3438 {
3439 if (SND_SOC_DAPM_EVENT_ON(event)) {
3440 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3441 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3442 0x0C);
3443 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3444 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3445 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3446 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3447 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3448 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3449 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3450 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3451 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3452 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3453 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3454 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3455 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3456 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3457 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3458 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3459 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3460 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3461 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3462 snd_soc_component_update_bits(comp,
3463 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3464 snd_soc_component_update_bits(comp,
3465 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3466 }
3467
3468 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3469 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3470 0x88);
3471 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3472 0x33);
3473 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3474 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3475 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3476 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3477 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3478 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3479 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3480 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3481 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3482 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3483 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3484 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3485 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3486 WCD9335_HPH_CONST_SEL_L_MASK,
3487 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3488 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3489 WCD9335_HPH_CONST_SEL_L_MASK,
3490 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3491 }
3492 }
3493
wcd9335_codec_hph_hifi_config(struct snd_soc_component * comp,int event)3494 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3495 int event)
3496 {
3497 if (SND_SOC_DAPM_EVENT_ON(event)) {
3498 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3499 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3500 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3501 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3502 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3503 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3504 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3505 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3506 0x0C);
3507 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3508 }
3509
3510 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3511 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3512 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3513 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3514 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3515 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3516 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3517 }
3518 }
3519
wcd9335_codec_hph_mode_config(struct snd_soc_component * component,int event,int mode)3520 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3521 int event, int mode)
3522 {
3523 switch (mode) {
3524 case CLS_H_LP:
3525 wcd9335_codec_hph_lp_config(component, event);
3526 break;
3527 case CLS_H_LOHIFI:
3528 wcd9335_codec_hph_lohifi_config(component, event);
3529 break;
3530 case CLS_H_HIFI:
3531 wcd9335_codec_hph_hifi_config(component, event);
3532 break;
3533 }
3534 }
3535
wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3536 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3537 struct snd_kcontrol *kc,
3538 int event)
3539 {
3540 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3541 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3542 int hph_mode = wcd->hph_mode;
3543 u8 dem_inp;
3544
3545 switch (event) {
3546 case SND_SOC_DAPM_PRE_PMU:
3547 /* Read DEM INP Select */
3548 dem_inp = snd_soc_component_read(comp,
3549 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3550 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3551 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3552 dev_err(comp->dev, "Incorrect DEM Input\n");
3553 return -EINVAL;
3554 }
3555 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3556 WCD_CLSH_STATE_HPHL,
3557 ((hph_mode == CLS_H_LOHIFI) ?
3558 CLS_H_HIFI : hph_mode));
3559
3560 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3561
3562 break;
3563 case SND_SOC_DAPM_POST_PMU:
3564 usleep_range(1000, 1100);
3565 break;
3566 case SND_SOC_DAPM_PRE_PMD:
3567 break;
3568 case SND_SOC_DAPM_POST_PMD:
3569 /* 1000us required as per HW requirement */
3570 usleep_range(1000, 1100);
3571
3572 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3573 WCD_CLSH_STATE_HPHR))
3574 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3575
3576 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3577 WCD_CLSH_STATE_HPHL,
3578 ((hph_mode == CLS_H_LOHIFI) ?
3579 CLS_H_HIFI : hph_mode));
3580 break;
3581 }
3582
3583 return 0;
3584 }
3585
wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3586 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3587 struct snd_kcontrol *kc, int event)
3588 {
3589 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3590 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3591
3592 switch (event) {
3593 case SND_SOC_DAPM_PRE_PMU:
3594 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3595 WCD_CLSH_STATE_LO, CLS_AB);
3596 break;
3597 case SND_SOC_DAPM_POST_PMD:
3598 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3599 WCD_CLSH_STATE_LO, CLS_AB);
3600 break;
3601 }
3602
3603 return 0;
3604 }
3605
wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3606 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3607 struct snd_kcontrol *kc, int event)
3608 {
3609 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3610 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3611
3612 switch (event) {
3613 case SND_SOC_DAPM_PRE_PMU:
3614 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3615 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3616
3617 break;
3618 case SND_SOC_DAPM_POST_PMD:
3619 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3620 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3621 break;
3622 }
3623
3624 return 0;
3625 }
3626
wcd9335_codec_hph_post_pa_config(struct wcd9335_codec * wcd,int mode,int event)3627 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3628 int mode, int event)
3629 {
3630 u8 scale_val = 0;
3631
3632 switch (event) {
3633 case SND_SOC_DAPM_POST_PMU:
3634 switch (mode) {
3635 case CLS_H_HIFI:
3636 scale_val = 0x3;
3637 break;
3638 case CLS_H_LOHIFI:
3639 scale_val = 0x1;
3640 break;
3641 }
3642 break;
3643 case SND_SOC_DAPM_PRE_PMD:
3644 scale_val = 0x6;
3645 break;
3646 }
3647
3648 if (scale_val)
3649 snd_soc_component_update_bits(wcd->component,
3650 WCD9335_HPH_PA_CTL1,
3651 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3652 scale_val << 1);
3653 if (SND_SOC_DAPM_EVENT_ON(event)) {
3654 if (wcd->comp_enabled[COMPANDER_1] ||
3655 wcd->comp_enabled[COMPANDER_2]) {
3656 /* GAIN Source Selection */
3657 snd_soc_component_update_bits(wcd->component,
3658 WCD9335_HPH_L_EN,
3659 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3660 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3661 snd_soc_component_update_bits(wcd->component,
3662 WCD9335_HPH_R_EN,
3663 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3664 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3665 snd_soc_component_update_bits(wcd->component,
3666 WCD9335_HPH_AUTO_CHOP,
3667 WCD9335_HPH_AUTO_CHOP_MASK,
3668 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3669 }
3670 snd_soc_component_update_bits(wcd->component,
3671 WCD9335_HPH_L_EN,
3672 WCD9335_HPH_PA_GAIN_MASK,
3673 wcd->hph_l_gain);
3674 snd_soc_component_update_bits(wcd->component,
3675 WCD9335_HPH_R_EN,
3676 WCD9335_HPH_PA_GAIN_MASK,
3677 wcd->hph_r_gain);
3678 }
3679
3680 if (SND_SOC_DAPM_EVENT_OFF(event))
3681 snd_soc_component_update_bits(wcd->component,
3682 WCD9335_HPH_AUTO_CHOP,
3683 WCD9335_HPH_AUTO_CHOP_MASK,
3684 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3685 }
3686
wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3687 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3688 struct snd_kcontrol *kc,
3689 int event)
3690 {
3691 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3692 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3693 int hph_mode = wcd->hph_mode;
3694 u8 dem_inp;
3695
3696 switch (event) {
3697 case SND_SOC_DAPM_PRE_PMU:
3698
3699 /* Read DEM INP Select */
3700 dem_inp = snd_soc_component_read(comp,
3701 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3702 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3703 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3704 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3705 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3706 hph_mode);
3707 return -EINVAL;
3708 }
3709
3710 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3711 WCD_CLSH_EVENT_PRE_DAC,
3712 WCD_CLSH_STATE_HPHR,
3713 ((hph_mode == CLS_H_LOHIFI) ?
3714 CLS_H_HIFI : hph_mode));
3715
3716 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3717
3718 break;
3719 case SND_SOC_DAPM_POST_PMD:
3720 /* 1000us required as per HW requirement */
3721 usleep_range(1000, 1100);
3722
3723 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3724 WCD_CLSH_STATE_HPHL))
3725 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3726
3727 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3728 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3729 CLS_H_HIFI : hph_mode));
3730 break;
3731 }
3732
3733 return 0;
3734 }
3735
wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3736 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3737 struct snd_kcontrol *kc,
3738 int event)
3739 {
3740 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3741 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3742 int hph_mode = wcd->hph_mode;
3743
3744 switch (event) {
3745 case SND_SOC_DAPM_PRE_PMU:
3746 break;
3747 case SND_SOC_DAPM_POST_PMU:
3748 /*
3749 * 7ms sleep is required after PA is enabled as per
3750 * HW requirement
3751 */
3752 usleep_range(7000, 7100);
3753
3754 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3755 snd_soc_component_update_bits(comp,
3756 WCD9335_CDC_RX1_RX_PATH_CTL,
3757 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3758 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3759
3760 /* Remove mix path mute if it is enabled */
3761 if ((snd_soc_component_read(comp,
3762 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3763 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3764 snd_soc_component_update_bits(comp,
3765 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3766 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3767 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3768
3769 break;
3770 case SND_SOC_DAPM_PRE_PMD:
3771 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3772 break;
3773 case SND_SOC_DAPM_POST_PMD:
3774 /* 5ms sleep is required after PA is disabled as per
3775 * HW requirement
3776 */
3777 usleep_range(5000, 5500);
3778 break;
3779 }
3780
3781 return 0;
3782 }
3783
wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3784 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3785 struct snd_kcontrol *kc,
3786 int event)
3787 {
3788 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3789 int vol_reg = 0, mix_vol_reg = 0;
3790
3791 if (w->reg == WCD9335_ANA_LO_1_2) {
3792 if (w->shift == 7) {
3793 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3794 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3795 } else if (w->shift == 6) {
3796 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3797 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3798 }
3799 } else if (w->reg == WCD9335_ANA_LO_3_4) {
3800 if (w->shift == 7) {
3801 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3802 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3803 } else if (w->shift == 6) {
3804 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3805 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3806 }
3807 } else {
3808 dev_err(comp->dev, "Error enabling lineout PA\n");
3809 return -EINVAL;
3810 }
3811
3812 switch (event) {
3813 case SND_SOC_DAPM_POST_PMU:
3814 /* 5ms sleep is required after PA is enabled as per
3815 * HW requirement
3816 */
3817 usleep_range(5000, 5500);
3818 snd_soc_component_update_bits(comp, vol_reg,
3819 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3820 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3821
3822 /* Remove mix path mute if it is enabled */
3823 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3824 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3825 snd_soc_component_update_bits(comp, mix_vol_reg,
3826 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3827 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3828 break;
3829 case SND_SOC_DAPM_POST_PMD:
3830 /* 5ms sleep is required after PA is disabled as per
3831 * HW requirement
3832 */
3833 usleep_range(5000, 5500);
3834 break;
3835 }
3836
3837 return 0;
3838 }
3839
wcd9335_codec_init_flyback(struct snd_soc_component * component)3840 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3841 {
3842 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3843 WCD9335_HPH_CONST_SEL_L_MASK,
3844 WCD9335_HPH_CONST_SEL_L_BYPASS);
3845 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3846 WCD9335_HPH_CONST_SEL_L_MASK,
3847 WCD9335_HPH_CONST_SEL_L_BYPASS);
3848 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3849 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3850 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3851 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3852 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3853 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3854 }
3855
wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3856 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3857 struct snd_kcontrol *kc, int event)
3858 {
3859 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3860 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3861
3862 switch (event) {
3863 case SND_SOC_DAPM_PRE_PMU:
3864 wcd->rx_bias_count++;
3865 if (wcd->rx_bias_count == 1) {
3866 wcd9335_codec_init_flyback(comp);
3867 snd_soc_component_update_bits(comp,
3868 WCD9335_ANA_RX_SUPPLIES,
3869 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3870 WCD9335_ANA_RX_BIAS_ENABLE);
3871 }
3872 break;
3873 case SND_SOC_DAPM_POST_PMD:
3874 wcd->rx_bias_count--;
3875 if (!wcd->rx_bias_count)
3876 snd_soc_component_update_bits(comp,
3877 WCD9335_ANA_RX_SUPPLIES,
3878 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3879 WCD9335_ANA_RX_BIAS_DISABLE);
3880 break;
3881 }
3882
3883 return 0;
3884 }
3885
wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3886 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3887 struct snd_kcontrol *kc, int event)
3888 {
3889 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3890 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3891 int hph_mode = wcd->hph_mode;
3892
3893 switch (event) {
3894 case SND_SOC_DAPM_PRE_PMU:
3895 break;
3896 case SND_SOC_DAPM_POST_PMU:
3897 /*
3898 * 7ms sleep is required after PA is enabled as per
3899 * HW requirement
3900 */
3901 usleep_range(7000, 7100);
3902 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3903 snd_soc_component_update_bits(comp,
3904 WCD9335_CDC_RX2_RX_PATH_CTL,
3905 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3906 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3907 /* Remove mix path mute if it is enabled */
3908 if ((snd_soc_component_read(comp,
3909 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3910 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3911 snd_soc_component_update_bits(comp,
3912 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3913 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3914 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3915
3916 break;
3917
3918 case SND_SOC_DAPM_PRE_PMD:
3919 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3920 break;
3921 case SND_SOC_DAPM_POST_PMD:
3922 /* 5ms sleep is required after PA is disabled as per
3923 * HW requirement
3924 */
3925 usleep_range(5000, 5500);
3926 break;
3927 }
3928
3929 return 0;
3930 }
3931
wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3932 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3933 struct snd_kcontrol *kc, int event)
3934 {
3935 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3936
3937 switch (event) {
3938 case SND_SOC_DAPM_POST_PMU:
3939 /* 5ms sleep is required after PA is enabled as per
3940 * HW requirement
3941 */
3942 usleep_range(5000, 5500);
3943 snd_soc_component_update_bits(comp,
3944 WCD9335_CDC_RX0_RX_PATH_CTL,
3945 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3946 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3947 /* Remove mix path mute if it is enabled */
3948 if ((snd_soc_component_read(comp,
3949 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3950 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3951 snd_soc_component_update_bits(comp,
3952 WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3953 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3954 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3955 break;
3956 case SND_SOC_DAPM_POST_PMD:
3957 /* 5ms sleep is required after PA is disabled as per
3958 * HW requirement
3959 */
3960 usleep_range(5000, 5500);
3961
3962 break;
3963 }
3964
3965 return 0;
3966 }
3967
wcd9335_slimbus_irq(int irq,void * data)3968 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3969 {
3970 struct wcd9335_codec *wcd = data;
3971 unsigned long status = 0;
3972 int i, j, port_id;
3973 unsigned int val, int_val = 0;
3974 irqreturn_t ret = IRQ_NONE;
3975 bool tx;
3976 unsigned short reg = 0;
3977
3978 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3979 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3980 regmap_read(wcd->if_regmap, i, &val);
3981 status |= ((u32)val << (8 * j));
3982 }
3983
3984 for_each_set_bit(j, &status, 32) {
3985 tx = (j >= 16);
3986 port_id = (tx ? j - 16 : j);
3987 regmap_read(wcd->if_regmap,
3988 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3989 if (val) {
3990 if (!tx)
3991 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3992 (port_id / 8);
3993 else
3994 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3995 (port_id / 8);
3996 regmap_read(
3997 wcd->if_regmap, reg, &int_val);
3998 /*
3999 * Ignore interrupts for ports for which the
4000 * interrupts are not specifically enabled.
4001 */
4002 if (!(int_val & (1 << (port_id % 8))))
4003 continue;
4004 }
4005
4006 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
4007 dev_err_ratelimited(wcd->dev,
4008 "%s: overflow error on %s port %d, value %x\n",
4009 __func__, (tx ? "TX" : "RX"), port_id, val);
4010
4011 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
4012 dev_err_ratelimited(wcd->dev,
4013 "%s: underflow error on %s port %d, value %x\n",
4014 __func__, (tx ? "TX" : "RX"), port_id, val);
4015
4016 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
4017 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
4018 if (!tx)
4019 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
4020 (port_id / 8);
4021 else
4022 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
4023 (port_id / 8);
4024 regmap_read(
4025 wcd->if_regmap, reg, &int_val);
4026 if (int_val & (1 << (port_id % 8))) {
4027 int_val = int_val ^ (1 << (port_id % 8));
4028 regmap_write(wcd->if_regmap,
4029 reg, int_val);
4030 }
4031 }
4032
4033 regmap_write(wcd->if_regmap,
4034 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
4035 BIT(j % 8));
4036 ret = IRQ_HANDLED;
4037 }
4038
4039 return ret;
4040 }
4041
4042 static struct wcd9335_irq wcd9335_irqs[] = {
4043 {
4044 .irq = WCD9335_IRQ_SLIMBUS,
4045 .handler = wcd9335_slimbus_irq,
4046 .name = "SLIM Slave",
4047 },
4048 };
4049
wcd9335_setup_irqs(struct wcd9335_codec * wcd)4050 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
4051 {
4052 int irq, ret, i;
4053
4054 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
4055 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
4056 if (irq < 0) {
4057 dev_err(wcd->dev, "Failed to get %s\n",
4058 wcd9335_irqs[i].name);
4059 return irq;
4060 }
4061
4062 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
4063 wcd9335_irqs[i].handler,
4064 IRQF_TRIGGER_RISING |
4065 IRQF_ONESHOT,
4066 wcd9335_irqs[i].name, wcd);
4067 if (ret) {
4068 dev_err(wcd->dev, "Failed to request %s\n",
4069 wcd9335_irqs[i].name);
4070 return ret;
4071 }
4072 }
4073
4074 /* enable interrupts on all slave ports */
4075 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4076 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4077 0xFF);
4078
4079 return ret;
4080 }
4081
wcd9335_teardown_irqs(struct wcd9335_codec * wcd)4082 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4083 {
4084 int i;
4085
4086 /* disable interrupts on all slave ports */
4087 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4088 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4089 0x00);
4090 }
4091
wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec * wcd,bool ccl_flag)4092 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4093 bool ccl_flag)
4094 {
4095 struct snd_soc_component *comp = wcd->component;
4096
4097 if (ccl_flag) {
4098 if (++wcd->sido_ccl_cnt == 1)
4099 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4100 WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4101 } else {
4102 if (wcd->sido_ccl_cnt == 0) {
4103 dev_err(wcd->dev, "sido_ccl already disabled\n");
4104 return;
4105 }
4106 if (--wcd->sido_ccl_cnt == 0)
4107 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4108 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4109 }
4110 }
4111
wcd9335_enable_master_bias(struct wcd9335_codec * wcd)4112 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4113 {
4114 wcd->master_bias_users++;
4115 if (wcd->master_bias_users == 1) {
4116 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4117 WCD9335_ANA_BIAS_EN_MASK,
4118 WCD9335_ANA_BIAS_ENABLE);
4119 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4120 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4121 WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4122 /*
4123 * 1ms delay is required after pre-charge is enabled
4124 * as per HW requirement
4125 */
4126 usleep_range(1000, 1100);
4127 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4128 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4129 WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4130 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4131 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4132 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4133 }
4134
4135 return 0;
4136 }
4137
wcd9335_enable_mclk(struct wcd9335_codec * wcd)4138 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4139 {
4140 /* Enable mclk requires master bias to be enabled first */
4141 if (wcd->master_bias_users <= 0)
4142 return -EINVAL;
4143
4144 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4145 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4146 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4147 wcd->clk_type);
4148 return -EINVAL;
4149 }
4150
4151 if (++wcd->clk_mclk_users == 1) {
4152 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4153 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4154 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4155 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4156 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4157 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4158 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4159 WCD9335_ANA_CLK_MCLK_EN_MASK,
4160 WCD9335_ANA_CLK_MCLK_ENABLE);
4161 regmap_update_bits(wcd->regmap,
4162 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4163 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4164 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4165 regmap_update_bits(wcd->regmap,
4166 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4167 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4168 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4169 /*
4170 * 10us sleep is required after clock is enabled
4171 * as per HW requirement
4172 */
4173 usleep_range(10, 15);
4174 }
4175
4176 wcd->clk_type = WCD_CLK_MCLK;
4177
4178 return 0;
4179 }
4180
wcd9335_disable_mclk(struct wcd9335_codec * wcd)4181 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4182 {
4183 if (wcd->clk_mclk_users <= 0)
4184 return -EINVAL;
4185
4186 if (--wcd->clk_mclk_users == 0) {
4187 if (wcd->clk_rco_users > 0) {
4188 /* MCLK to RCO switch */
4189 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4190 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4191 WCD9335_ANA_CLK_MCLK_SRC_RCO);
4192 wcd->clk_type = WCD_CLK_RCO;
4193 } else {
4194 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4195 WCD9335_ANA_CLK_MCLK_EN_MASK,
4196 WCD9335_ANA_CLK_MCLK_DISABLE);
4197 wcd->clk_type = WCD_CLK_OFF;
4198 }
4199
4200 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4201 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4202 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4203 }
4204
4205 return 0;
4206 }
4207
wcd9335_disable_master_bias(struct wcd9335_codec * wcd)4208 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4209 {
4210 if (wcd->master_bias_users <= 0)
4211 return -EINVAL;
4212
4213 wcd->master_bias_users--;
4214 if (wcd->master_bias_users == 0) {
4215 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4216 WCD9335_ANA_BIAS_EN_MASK,
4217 WCD9335_ANA_BIAS_DISABLE);
4218 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4219 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4220 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4221 }
4222 return 0;
4223 }
4224
wcd9335_cdc_req_mclk_enable(struct wcd9335_codec * wcd,bool enable)4225 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4226 bool enable)
4227 {
4228 int ret = 0;
4229
4230 if (enable) {
4231 wcd9335_cdc_sido_ccl_enable(wcd, true);
4232 ret = clk_prepare_enable(wcd->mclk);
4233 if (ret) {
4234 dev_err(wcd->dev, "%s: ext clk enable failed\n",
4235 __func__);
4236 goto err;
4237 }
4238 /* get BG */
4239 wcd9335_enable_master_bias(wcd);
4240 /* get MCLK */
4241 wcd9335_enable_mclk(wcd);
4242
4243 } else {
4244 /* put MCLK */
4245 wcd9335_disable_mclk(wcd);
4246 /* put BG */
4247 wcd9335_disable_master_bias(wcd);
4248 clk_disable_unprepare(wcd->mclk);
4249 wcd9335_cdc_sido_ccl_enable(wcd, false);
4250 }
4251 err:
4252 return ret;
4253 }
4254
wcd9335_codec_apply_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4255 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4256 enum wcd9335_sido_voltage req_mv)
4257 {
4258 struct snd_soc_component *comp = wcd->component;
4259 int vout_d_val;
4260
4261 if (req_mv == wcd->sido_voltage)
4262 return;
4263
4264 /* compute the vout_d step value */
4265 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4266 WCD9335_ANA_BUCK_VOUT_MASK;
4267 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4268 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4269 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4270 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4271
4272 /* 1 msec sleep required after SIDO Vout_D voltage change */
4273 usleep_range(1000, 1100);
4274 wcd->sido_voltage = req_mv;
4275 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4276 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4277 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4278 }
4279
wcd9335_codec_update_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4280 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4281 enum wcd9335_sido_voltage req_mv)
4282 {
4283 int ret = 0;
4284
4285 /* enable mclk before setting SIDO voltage */
4286 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4287 if (ret) {
4288 dev_err(wcd->dev, "Ext clk enable failed\n");
4289 goto err;
4290 }
4291
4292 wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4293 wcd9335_cdc_req_mclk_enable(wcd, false);
4294
4295 err:
4296 return ret;
4297 }
4298
_wcd9335_codec_enable_mclk(struct snd_soc_component * component,int enable)4299 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4300 int enable)
4301 {
4302 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4303 int ret;
4304
4305 if (enable) {
4306 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4307 if (ret)
4308 return ret;
4309
4310 wcd9335_codec_apply_sido_voltage(wcd,
4311 SIDO_VOLTAGE_NOMINAL_MV);
4312 } else {
4313 wcd9335_codec_update_sido_voltage(wcd,
4314 wcd->sido_voltage);
4315 wcd9335_cdc_req_mclk_enable(wcd, false);
4316 }
4317
4318 return 0;
4319 }
4320
wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4321 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4322 struct snd_kcontrol *kc, int event)
4323 {
4324 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4325
4326 switch (event) {
4327 case SND_SOC_DAPM_PRE_PMU:
4328 return _wcd9335_codec_enable_mclk(comp, true);
4329 case SND_SOC_DAPM_POST_PMD:
4330 return _wcd9335_codec_enable_mclk(comp, false);
4331 }
4332
4333 return 0;
4334 }
4335
4336 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4337 /* TODO SPK1 & SPK2 OUT*/
4338 SND_SOC_DAPM_OUTPUT("EAR"),
4339 SND_SOC_DAPM_OUTPUT("HPHL"),
4340 SND_SOC_DAPM_OUTPUT("HPHR"),
4341 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4342 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4343 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4344 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4345 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4346 AIF1_PB, 0, wcd9335_codec_enable_slim,
4347 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4348 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4349 AIF2_PB, 0, wcd9335_codec_enable_slim,
4350 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4351 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4352 AIF3_PB, 0, wcd9335_codec_enable_slim,
4353 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4354 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4355 AIF4_PB, 0, wcd9335_codec_enable_slim,
4356 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4357 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4358 &slim_rx_mux[WCD9335_RX0]),
4359 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4360 &slim_rx_mux[WCD9335_RX1]),
4361 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4362 &slim_rx_mux[WCD9335_RX2]),
4363 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4364 &slim_rx_mux[WCD9335_RX3]),
4365 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4366 &slim_rx_mux[WCD9335_RX4]),
4367 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4368 &slim_rx_mux[WCD9335_RX5]),
4369 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4370 &slim_rx_mux[WCD9335_RX6]),
4371 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4372 &slim_rx_mux[WCD9335_RX7]),
4373 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4374 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4375 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4376 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4377 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4378 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4379 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4380 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4381 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4382 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4383 SND_SOC_DAPM_POST_PMU),
4384 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4385 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4386 SND_SOC_DAPM_POST_PMU),
4387 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4388 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4389 SND_SOC_DAPM_POST_PMU),
4390 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4391 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4392 SND_SOC_DAPM_POST_PMU),
4393 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4394 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4395 SND_SOC_DAPM_POST_PMU),
4396 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4397 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4398 SND_SOC_DAPM_POST_PMU),
4399 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4400 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4401 SND_SOC_DAPM_POST_PMU),
4402 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4403 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4404 SND_SOC_DAPM_POST_PMU),
4405 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4406 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4407 SND_SOC_DAPM_POST_PMU),
4408 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4409 &rx_int0_1_mix_inp0_mux),
4410 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4411 &rx_int0_1_mix_inp1_mux),
4412 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4413 &rx_int0_1_mix_inp2_mux),
4414 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4415 &rx_int1_1_mix_inp0_mux),
4416 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4417 &rx_int1_1_mix_inp1_mux),
4418 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4419 &rx_int1_1_mix_inp2_mux),
4420 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4421 &rx_int2_1_mix_inp0_mux),
4422 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4423 &rx_int2_1_mix_inp1_mux),
4424 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4425 &rx_int2_1_mix_inp2_mux),
4426 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4427 &rx_int3_1_mix_inp0_mux),
4428 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4429 &rx_int3_1_mix_inp1_mux),
4430 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4431 &rx_int3_1_mix_inp2_mux),
4432 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4433 &rx_int4_1_mix_inp0_mux),
4434 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4435 &rx_int4_1_mix_inp1_mux),
4436 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4437 &rx_int4_1_mix_inp2_mux),
4438 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4439 &rx_int5_1_mix_inp0_mux),
4440 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4441 &rx_int5_1_mix_inp1_mux),
4442 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4443 &rx_int5_1_mix_inp2_mux),
4444 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4445 &rx_int6_1_mix_inp0_mux),
4446 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4447 &rx_int6_1_mix_inp1_mux),
4448 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4449 &rx_int6_1_mix_inp2_mux),
4450 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4451 &rx_int7_1_mix_inp0_mux),
4452 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4453 &rx_int7_1_mix_inp1_mux),
4454 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4455 &rx_int7_1_mix_inp2_mux),
4456 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4457 &rx_int8_1_mix_inp0_mux),
4458 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4459 &rx_int8_1_mix_inp1_mux),
4460 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4461 &rx_int8_1_mix_inp2_mux),
4462
4463 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4464 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4465 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4466 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4467 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4468 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4469 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4470 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4471 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4472 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4473 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4474 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4475 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4476 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4477 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4478 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4479 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4480 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4481
4482 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4483 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4484 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4485 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4486 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4487 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4488 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4489 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4490 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4491
4492 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4493 &rx_int0_dem_inp_mux),
4494 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4495 &rx_int1_dem_inp_mux),
4496 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4497 &rx_int2_dem_inp_mux),
4498
4499 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4500 INTERP_EAR, 0, &rx_int0_interp_mux,
4501 wcd9335_codec_enable_interpolator,
4502 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4503 SND_SOC_DAPM_POST_PMD),
4504 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4505 INTERP_HPHL, 0, &rx_int1_interp_mux,
4506 wcd9335_codec_enable_interpolator,
4507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4508 SND_SOC_DAPM_POST_PMD),
4509 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4510 INTERP_HPHR, 0, &rx_int2_interp_mux,
4511 wcd9335_codec_enable_interpolator,
4512 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4513 SND_SOC_DAPM_POST_PMD),
4514 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4515 INTERP_LO1, 0, &rx_int3_interp_mux,
4516 wcd9335_codec_enable_interpolator,
4517 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4518 SND_SOC_DAPM_POST_PMD),
4519 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4520 INTERP_LO2, 0, &rx_int4_interp_mux,
4521 wcd9335_codec_enable_interpolator,
4522 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4523 SND_SOC_DAPM_POST_PMD),
4524 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4525 INTERP_LO3, 0, &rx_int5_interp_mux,
4526 wcd9335_codec_enable_interpolator,
4527 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4528 SND_SOC_DAPM_POST_PMD),
4529 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4530 INTERP_LO4, 0, &rx_int6_interp_mux,
4531 wcd9335_codec_enable_interpolator,
4532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4533 SND_SOC_DAPM_POST_PMD),
4534 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4535 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4536 wcd9335_codec_enable_interpolator,
4537 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4538 SND_SOC_DAPM_POST_PMD),
4539 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4540 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4541 wcd9335_codec_enable_interpolator,
4542 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4543 SND_SOC_DAPM_POST_PMD),
4544
4545 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4546 0, 0, wcd9335_codec_ear_dac_event,
4547 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4548 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4549 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4550 5, 0, wcd9335_codec_hphl_dac_event,
4551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4552 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4553 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4554 4, 0, wcd9335_codec_hphr_dac_event,
4555 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4556 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4557 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4558 0, 0, wcd9335_codec_lineout_dac_event,
4559 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4560 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4561 0, 0, wcd9335_codec_lineout_dac_event,
4562 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4563 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4564 0, 0, wcd9335_codec_lineout_dac_event,
4565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4566 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4567 0, 0, wcd9335_codec_lineout_dac_event,
4568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4569 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4570 wcd9335_codec_enable_hphl_pa,
4571 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4572 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4573 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4574 wcd9335_codec_enable_hphr_pa,
4575 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4576 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4577 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4578 wcd9335_codec_enable_ear_pa,
4579 SND_SOC_DAPM_POST_PMU |
4580 SND_SOC_DAPM_POST_PMD),
4581 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4582 wcd9335_codec_enable_lineout_pa,
4583 SND_SOC_DAPM_POST_PMU |
4584 SND_SOC_DAPM_POST_PMD),
4585 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4586 wcd9335_codec_enable_lineout_pa,
4587 SND_SOC_DAPM_POST_PMU |
4588 SND_SOC_DAPM_POST_PMD),
4589 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4590 wcd9335_codec_enable_lineout_pa,
4591 SND_SOC_DAPM_POST_PMU |
4592 SND_SOC_DAPM_POST_PMD),
4593 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4594 wcd9335_codec_enable_lineout_pa,
4595 SND_SOC_DAPM_POST_PMU |
4596 SND_SOC_DAPM_POST_PMD),
4597 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4598 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4599 SND_SOC_DAPM_POST_PMD),
4600 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4601 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4602 SND_SOC_DAPM_POST_PMD),
4603
4604 /* TX */
4605 SND_SOC_DAPM_INPUT("AMIC1"),
4606 SND_SOC_DAPM_INPUT("AMIC2"),
4607 SND_SOC_DAPM_INPUT("AMIC3"),
4608 SND_SOC_DAPM_INPUT("AMIC4"),
4609 SND_SOC_DAPM_INPUT("AMIC5"),
4610 SND_SOC_DAPM_INPUT("AMIC6"),
4611
4612 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4613 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4614 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4615
4616 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4617 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4618 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4619
4620 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4621 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4622 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4623
4624 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4625 wcd9335_codec_enable_micbias,
4626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4627 SND_SOC_DAPM_POST_PMD),
4628 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4629 wcd9335_codec_enable_micbias,
4630 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4631 SND_SOC_DAPM_POST_PMD),
4632 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4633 wcd9335_codec_enable_micbias,
4634 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4635 SND_SOC_DAPM_POST_PMD),
4636 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4637 wcd9335_codec_enable_micbias,
4638 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4639 SND_SOC_DAPM_POST_PMD),
4640
4641 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4642 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4643 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4644 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4645 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4646 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4647 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4648 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4649 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4650 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4651 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4652 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4653
4654 /* Digital Mic Inputs */
4655 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4656 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4657 SND_SOC_DAPM_POST_PMD),
4658
4659 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4660 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4661 SND_SOC_DAPM_POST_PMD),
4662
4663 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4664 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4665 SND_SOC_DAPM_POST_PMD),
4666
4667 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4668 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4669 SND_SOC_DAPM_POST_PMD),
4670
4671 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4672 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4673 SND_SOC_DAPM_POST_PMD),
4674
4675 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4676 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4677 SND_SOC_DAPM_POST_PMD),
4678
4679 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4680 &tx_dmic_mux0),
4681 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4682 &tx_dmic_mux1),
4683 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4684 &tx_dmic_mux2),
4685 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4686 &tx_dmic_mux3),
4687 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4688 &tx_dmic_mux4),
4689 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4690 &tx_dmic_mux5),
4691 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4692 &tx_dmic_mux6),
4693 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4694 &tx_dmic_mux7),
4695 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4696 &tx_dmic_mux8),
4697
4698 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4699 &tx_amic_mux0),
4700 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4701 &tx_amic_mux1),
4702 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4703 &tx_amic_mux2),
4704 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4705 &tx_amic_mux3),
4706 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4707 &tx_amic_mux4),
4708 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4709 &tx_amic_mux5),
4710 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4711 &tx_amic_mux6),
4712 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4713 &tx_amic_mux7),
4714 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4715 &tx_amic_mux8),
4716
4717 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4718 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4719
4720 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4721 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4722
4723 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4724 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4725
4726 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4727 &sb_tx0_mux),
4728 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4729 &sb_tx1_mux),
4730 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4731 &sb_tx2_mux),
4732 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4733 &sb_tx3_mux),
4734 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4735 &sb_tx4_mux),
4736 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4737 &sb_tx5_mux),
4738 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4739 &sb_tx6_mux),
4740 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4741 &sb_tx7_mux),
4742 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4743 &sb_tx8_mux),
4744
4745 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4746 &tx_adc_mux0, wcd9335_codec_enable_dec,
4747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4748 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4749
4750 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4751 &tx_adc_mux1, wcd9335_codec_enable_dec,
4752 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4753 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4754
4755 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4756 &tx_adc_mux2, wcd9335_codec_enable_dec,
4757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4758 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4759
4760 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4761 &tx_adc_mux3, wcd9335_codec_enable_dec,
4762 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4763 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4764
4765 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4766 &tx_adc_mux4, wcd9335_codec_enable_dec,
4767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4768 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4769
4770 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4771 &tx_adc_mux5, wcd9335_codec_enable_dec,
4772 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4773 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4774
4775 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4776 &tx_adc_mux6, wcd9335_codec_enable_dec,
4777 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4778 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4779
4780 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4781 &tx_adc_mux7, wcd9335_codec_enable_dec,
4782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4783 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4784
4785 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4786 &tx_adc_mux8, wcd9335_codec_enable_dec,
4787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4788 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4789 };
4790
wcd9335_enable_sido_buck(struct snd_soc_component * component)4791 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4792 {
4793 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4794
4795 snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4796 WCD9335_ANA_RCO_BG_EN_MASK,
4797 WCD9335_ANA_RCO_BG_ENABLE);
4798 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4799 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4800 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4801 /* 100us sleep needed after IREF settings */
4802 usleep_range(100, 110);
4803 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4804 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4805 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4806 /* 100us sleep needed after VREF settings */
4807 usleep_range(100, 110);
4808 wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4809 }
4810
wcd9335_enable_efuse_sensing(struct snd_soc_component * comp)4811 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4812 {
4813 _wcd9335_codec_enable_mclk(comp, true);
4814 snd_soc_component_update_bits(comp,
4815 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4816 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4817 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4818 /*
4819 * 5ms sleep required after enabling efuse control
4820 * before checking the status.
4821 */
4822 usleep_range(5000, 5500);
4823
4824 if (!(snd_soc_component_read(comp,
4825 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4826 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4827 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4828
4829 wcd9335_enable_sido_buck(comp);
4830 _wcd9335_codec_enable_mclk(comp, false);
4831
4832 return 0;
4833 }
4834
wcd9335_codec_init(struct snd_soc_component * component)4835 static void wcd9335_codec_init(struct snd_soc_component *component)
4836 {
4837 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4838 int i;
4839
4840 /* ungate MCLK and set clk rate */
4841 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4842 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4843
4844 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4845 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4846 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4847
4848 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4849 snd_soc_component_update_bits(component,
4850 wcd9335_codec_reg_init[i].reg,
4851 wcd9335_codec_reg_init[i].mask,
4852 wcd9335_codec_reg_init[i].val);
4853
4854 wcd9335_enable_efuse_sensing(component);
4855 }
4856
wcd9335_codec_probe(struct snd_soc_component * component)4857 static int wcd9335_codec_probe(struct snd_soc_component *component)
4858 {
4859 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4860 int ret;
4861 int i;
4862
4863 snd_soc_component_init_regmap(component, wcd->regmap);
4864 /* Class-H Init*/
4865 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4866 if (IS_ERR(wcd->clsh_ctrl))
4867 return PTR_ERR(wcd->clsh_ctrl);
4868
4869 /* Default HPH Mode to Class-H HiFi */
4870 wcd->hph_mode = CLS_H_HIFI;
4871 wcd->component = component;
4872
4873 wcd9335_codec_init(component);
4874
4875 for (i = 0; i < NUM_CODEC_DAIS; i++)
4876 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4877
4878 ret = wcd9335_setup_irqs(wcd);
4879 if (ret)
4880 goto free_clsh_ctrl;
4881
4882 return 0;
4883
4884 free_clsh_ctrl:
4885 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4886 return ret;
4887 }
4888
wcd9335_codec_remove(struct snd_soc_component * comp)4889 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4890 {
4891 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4892
4893 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4894 wcd9335_teardown_irqs(wcd);
4895 }
4896
wcd9335_codec_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)4897 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4898 int clk_id, int source,
4899 unsigned int freq, int dir)
4900 {
4901 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4902
4903 wcd->mclk_rate = freq;
4904
4905 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4906 snd_soc_component_update_bits(comp,
4907 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4908 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4909 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4910 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4911 snd_soc_component_update_bits(comp,
4912 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4913 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4914 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4915
4916 return clk_set_rate(wcd->mclk, freq);
4917 }
4918
4919 static const struct snd_soc_component_driver wcd9335_component_drv = {
4920 .probe = wcd9335_codec_probe,
4921 .remove = wcd9335_codec_remove,
4922 .set_sysclk = wcd9335_codec_set_sysclk,
4923 .controls = wcd9335_snd_controls,
4924 .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4925 .dapm_widgets = wcd9335_dapm_widgets,
4926 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4927 .dapm_routes = wcd9335_audio_map,
4928 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4929 .endianness = 1,
4930 };
4931
wcd9335_probe(struct wcd9335_codec * wcd)4932 static int wcd9335_probe(struct wcd9335_codec *wcd)
4933 {
4934 struct device *dev = wcd->dev;
4935
4936 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4937 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4938
4939 wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4940 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4941
4942 return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4943 wcd9335_slim_dais,
4944 ARRAY_SIZE(wcd9335_slim_dais));
4945 }
4946
4947 static const struct regmap_range_cfg wcd9335_ranges[] = {
4948 {
4949 .name = "WCD9335",
4950 .range_min = 0x0,
4951 .range_max = WCD9335_MAX_REGISTER,
4952 .selector_reg = WCD9335_SEL_REGISTER,
4953 .selector_mask = 0xff,
4954 .selector_shift = 0,
4955 .window_start = 0x800,
4956 .window_len = 0x100,
4957 },
4958 };
4959
wcd9335_is_volatile_register(struct device * dev,unsigned int reg)4960 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4961 {
4962 switch (reg) {
4963 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4964 case WCD9335_ANA_MBHC_RESULT_3:
4965 case WCD9335_ANA_MBHC_RESULT_2:
4966 case WCD9335_ANA_MBHC_RESULT_1:
4967 case WCD9335_ANA_MBHC_MECH:
4968 case WCD9335_ANA_MBHC_ELECT:
4969 case WCD9335_ANA_MBHC_ZDET:
4970 case WCD9335_ANA_MICB2:
4971 case WCD9335_ANA_RCO:
4972 case WCD9335_ANA_BIAS:
4973 return true;
4974 default:
4975 return false;
4976 }
4977 }
4978
4979 static struct regmap_config wcd9335_regmap_config = {
4980 .reg_bits = 16,
4981 .val_bits = 8,
4982 .cache_type = REGCACHE_RBTREE,
4983 .max_register = WCD9335_MAX_REGISTER,
4984 .can_multi_write = true,
4985 .ranges = wcd9335_ranges,
4986 .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4987 .volatile_reg = wcd9335_is_volatile_register,
4988 };
4989
4990 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4991 {
4992 .name = "WCD9335-IFC-DEV",
4993 .range_min = 0x0,
4994 .range_max = WCD9335_MAX_REGISTER,
4995 .selector_reg = WCD9335_SEL_REGISTER,
4996 .selector_mask = 0xfff,
4997 .selector_shift = 0,
4998 .window_start = 0x800,
4999 .window_len = 0x400,
5000 },
5001 };
5002
5003 static struct regmap_config wcd9335_ifc_regmap_config = {
5004 .reg_bits = 16,
5005 .val_bits = 8,
5006 .can_multi_write = true,
5007 .max_register = WCD9335_MAX_REGISTER,
5008 .ranges = wcd9335_ifc_ranges,
5009 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
5010 };
5011
5012 static const struct regmap_irq wcd9335_codec_irqs[] = {
5013 /* INTR_REG 0 */
5014 [WCD9335_IRQ_SLIMBUS] = {
5015 .reg_offset = 0,
5016 .mask = BIT(0),
5017 .type = {
5018 .type_reg_offset = 0,
5019 .types_supported = IRQ_TYPE_EDGE_BOTH,
5020 .type_reg_mask = BIT(0),
5021 },
5022 },
5023 };
5024
5025 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
5026 .name = "wcd9335_pin1_irq",
5027 .status_base = WCD9335_INTR_PIN1_STATUS0,
5028 .mask_base = WCD9335_INTR_PIN1_MASK0,
5029 .ack_base = WCD9335_INTR_PIN1_CLEAR0,
5030 .type_base = WCD9335_INTR_LEVEL0,
5031 .num_type_reg = 4,
5032 .num_regs = 4,
5033 .irqs = wcd9335_codec_irqs,
5034 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
5035 };
5036
wcd9335_parse_dt(struct wcd9335_codec * wcd)5037 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
5038 {
5039 struct device *dev = wcd->dev;
5040 struct device_node *np = dev->of_node;
5041 int ret;
5042
5043 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
5044 if (wcd->reset_gpio < 0) {
5045 dev_err(dev, "Reset GPIO missing from DT\n");
5046 return wcd->reset_gpio;
5047 }
5048
5049 wcd->mclk = devm_clk_get(dev, "mclk");
5050 if (IS_ERR(wcd->mclk)) {
5051 dev_err(dev, "mclk not found\n");
5052 return PTR_ERR(wcd->mclk);
5053 }
5054
5055 wcd->native_clk = devm_clk_get(dev, "slimbus");
5056 if (IS_ERR(wcd->native_clk)) {
5057 dev_err(dev, "slimbus clock not found\n");
5058 return PTR_ERR(wcd->native_clk);
5059 }
5060
5061 wcd->supplies[0].supply = "vdd-buck";
5062 wcd->supplies[1].supply = "vdd-buck-sido";
5063 wcd->supplies[2].supply = "vdd-tx";
5064 wcd->supplies[3].supply = "vdd-rx";
5065 wcd->supplies[4].supply = "vdd-io";
5066
5067 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
5068 if (ret) {
5069 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5070 return ret;
5071 }
5072
5073 return 0;
5074 }
5075
wcd9335_power_on_reset(struct wcd9335_codec * wcd)5076 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5077 {
5078 struct device *dev = wcd->dev;
5079 int ret;
5080
5081 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
5082 if (ret) {
5083 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5084 return ret;
5085 }
5086
5087 /*
5088 * For WCD9335, it takes about 600us for the Vout_A and
5089 * Vout_D to be ready after BUCK_SIDO is powered up.
5090 * SYS_RST_N shouldn't be pulled high during this time
5091 * Toggle the reset line to make sure the reset pulse is
5092 * correctly applied
5093 */
5094 usleep_range(600, 650);
5095
5096 gpio_direction_output(wcd->reset_gpio, 0);
5097 msleep(20);
5098 gpio_set_value(wcd->reset_gpio, 1);
5099 msleep(20);
5100
5101 return 0;
5102 }
5103
wcd9335_bring_up(struct wcd9335_codec * wcd)5104 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5105 {
5106 struct regmap *rm = wcd->regmap;
5107 int val, byte0;
5108
5109 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5110 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5111
5112 if ((val < 0) || (byte0 < 0)) {
5113 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5114 return -EINVAL;
5115 }
5116
5117 if (byte0 == 0x1) {
5118 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5119 wcd->version = WCD9335_VERSION_2_0;
5120 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5121 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5122 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5123 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5124 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5125 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5126 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5127 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5128 } else {
5129 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5130 return -EINVAL;
5131 }
5132
5133 return 0;
5134 }
5135
wcd9335_irq_init(struct wcd9335_codec * wcd)5136 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5137 {
5138 int ret;
5139
5140 /*
5141 * INTR1 consists of all possible interrupt sources Ear OCP,
5142 * HPH OCP, MBHC, MAD, VBAT, and SVA
5143 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5144 */
5145 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5146 if (wcd->intr1 < 0) {
5147 if (wcd->intr1 != -EPROBE_DEFER)
5148 dev_err(wcd->dev, "Unable to configure IRQ\n");
5149
5150 return wcd->intr1;
5151 }
5152
5153 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5154 IRQF_TRIGGER_HIGH, 0,
5155 &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5156 if (ret)
5157 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret);
5158
5159 return ret;
5160 }
5161
wcd9335_slim_probe(struct slim_device * slim)5162 static int wcd9335_slim_probe(struct slim_device *slim)
5163 {
5164 struct device *dev = &slim->dev;
5165 struct wcd9335_codec *wcd;
5166 int ret;
5167
5168 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5169 if (!wcd)
5170 return -ENOMEM;
5171
5172 wcd->dev = dev;
5173 ret = wcd9335_parse_dt(wcd);
5174 if (ret) {
5175 dev_err(dev, "Error parsing DT: %d\n", ret);
5176 return ret;
5177 }
5178
5179 ret = wcd9335_power_on_reset(wcd);
5180 if (ret)
5181 return ret;
5182
5183 dev_set_drvdata(dev, wcd);
5184
5185 return 0;
5186 }
5187
wcd9335_slim_status(struct slim_device * sdev,enum slim_device_status status)5188 static int wcd9335_slim_status(struct slim_device *sdev,
5189 enum slim_device_status status)
5190 {
5191 struct device *dev = &sdev->dev;
5192 struct device_node *ifc_dev_np;
5193 struct wcd9335_codec *wcd;
5194 int ret;
5195
5196 wcd = dev_get_drvdata(dev);
5197
5198 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5199 if (!ifc_dev_np) {
5200 dev_err(dev, "No Interface device found\n");
5201 return -EINVAL;
5202 }
5203
5204 wcd->slim = sdev;
5205 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5206 of_node_put(ifc_dev_np);
5207 if (!wcd->slim_ifc_dev) {
5208 dev_err(dev, "Unable to get SLIM Interface device\n");
5209 return -EINVAL;
5210 }
5211
5212 slim_get_logical_addr(wcd->slim_ifc_dev);
5213
5214 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5215 if (IS_ERR(wcd->regmap)) {
5216 dev_err(dev, "Failed to allocate slim register map\n");
5217 return PTR_ERR(wcd->regmap);
5218 }
5219
5220 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5221 &wcd9335_ifc_regmap_config);
5222 if (IS_ERR(wcd->if_regmap)) {
5223 dev_err(dev, "Failed to allocate ifc register map\n");
5224 return PTR_ERR(wcd->if_regmap);
5225 }
5226
5227 ret = wcd9335_bring_up(wcd);
5228 if (ret) {
5229 dev_err(dev, "Failed to bringup WCD9335\n");
5230 return ret;
5231 }
5232
5233 ret = wcd9335_irq_init(wcd);
5234 if (ret)
5235 return ret;
5236
5237 wcd9335_probe(wcd);
5238
5239 return 0;
5240 }
5241
5242 static const struct slim_device_id wcd9335_slim_id[] = {
5243 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5244 {}
5245 };
5246 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5247
5248 static struct slim_driver wcd9335_slim_driver = {
5249 .driver = {
5250 .name = "wcd9335-slim",
5251 },
5252 .probe = wcd9335_slim_probe,
5253 .device_status = wcd9335_slim_status,
5254 .id_table = wcd9335_slim_id,
5255 };
5256
5257 module_slim_driver(wcd9335_slim_driver);
5258 MODULE_DESCRIPTION("WCD9335 slim driver");
5259 MODULE_LICENSE("GPL v2");
5260 MODULE_ALIAS("slim:217:1a0:*");
5261