1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  linux/drivers/mmc/host/wbsd.h - Winbond W83L51xD SD/MMC driver
4  *
5  *  Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved.
6  */
7 
8 #define LOCK_CODE		0xAA
9 
10 #define WBSD_CONF_SWRST		0x02
11 #define WBSD_CONF_DEVICE	0x07
12 #define WBSD_CONF_ID_HI		0x20
13 #define WBSD_CONF_ID_LO		0x21
14 #define WBSD_CONF_POWER		0x22
15 #define WBSD_CONF_PME		0x23
16 #define WBSD_CONF_PMES		0x24
17 
18 #define WBSD_CONF_ENABLE	0x30
19 #define WBSD_CONF_PORT_HI	0x60
20 #define WBSD_CONF_PORT_LO	0x61
21 #define WBSD_CONF_IRQ		0x70
22 #define WBSD_CONF_DRQ		0x74
23 
24 #define WBSD_CONF_PINS		0xF0
25 
26 #define DEVICE_SD		0x03
27 
28 #define WBSD_PINS_DAT3_HI	0x20
29 #define WBSD_PINS_DAT3_OUT	0x10
30 #define WBSD_PINS_GP11_HI	0x04
31 #define WBSD_PINS_DETECT_GP11	0x02
32 #define WBSD_PINS_DETECT_DAT3	0x01
33 
34 #define WBSD_CMDR		0x00
35 #define WBSD_DFR		0x01
36 #define WBSD_EIR		0x02
37 #define WBSD_ISR		0x03
38 #define WBSD_FSR		0x04
39 #define WBSD_IDXR		0x05
40 #define WBSD_DATAR		0x06
41 #define WBSD_CSR		0x07
42 
43 #define WBSD_EINT_CARD		0x40
44 #define WBSD_EINT_FIFO_THRE	0x20
45 #define WBSD_EINT_CRC		0x10
46 #define WBSD_EINT_TIMEOUT	0x08
47 #define WBSD_EINT_PROGEND	0x04
48 #define WBSD_EINT_BUSYEND	0x02
49 #define WBSD_EINT_TC		0x01
50 
51 #define WBSD_INT_PENDING	0x80
52 #define WBSD_INT_CARD		0x40
53 #define WBSD_INT_FIFO_THRE	0x20
54 #define WBSD_INT_CRC		0x10
55 #define WBSD_INT_TIMEOUT	0x08
56 #define WBSD_INT_PROGEND	0x04
57 #define WBSD_INT_BUSYEND	0x02
58 #define WBSD_INT_TC		0x01
59 
60 #define WBSD_FIFO_EMPTY		0x80
61 #define WBSD_FIFO_FULL		0x40
62 #define WBSD_FIFO_EMTHRE	0x20
63 #define WBSD_FIFO_FUTHRE	0x10
64 #define WBSD_FIFO_SZMASK	0x0F
65 
66 #define WBSD_MSLED		0x20
67 #define WBSD_POWER_N		0x10
68 #define WBSD_WRPT		0x04
69 #define WBSD_CARDPRESENT	0x01
70 
71 #define WBSD_IDX_CLK		0x01
72 #define WBSD_IDX_PBSMSB		0x02
73 #define WBSD_IDX_TAAC		0x03
74 #define WBSD_IDX_NSAC		0x04
75 #define WBSD_IDX_PBSLSB		0x05
76 #define WBSD_IDX_SETUP		0x06
77 #define WBSD_IDX_DMA		0x07
78 #define WBSD_IDX_FIFOEN		0x08
79 #define WBSD_IDX_STATUS		0x10
80 #define WBSD_IDX_RSPLEN		0x1E
81 #define WBSD_IDX_RESP0		0x1F
82 #define WBSD_IDX_RESP1		0x20
83 #define WBSD_IDX_RESP2		0x21
84 #define WBSD_IDX_RESP3		0x22
85 #define WBSD_IDX_RESP4		0x23
86 #define WBSD_IDX_RESP5		0x24
87 #define WBSD_IDX_RESP6		0x25
88 #define WBSD_IDX_RESP7		0x26
89 #define WBSD_IDX_RESP8		0x27
90 #define WBSD_IDX_RESP9		0x28
91 #define WBSD_IDX_RESP10		0x29
92 #define WBSD_IDX_RESP11		0x2A
93 #define WBSD_IDX_RESP12		0x2B
94 #define WBSD_IDX_RESP13		0x2C
95 #define WBSD_IDX_RESP14		0x2D
96 #define WBSD_IDX_RESP15		0x2E
97 #define WBSD_IDX_RESP16		0x2F
98 #define WBSD_IDX_CRCSTATUS	0x30
99 #define WBSD_IDX_ISR		0x3F
100 
101 #define WBSD_CLK_375K		0x00
102 #define WBSD_CLK_12M		0x01
103 #define WBSD_CLK_16M		0x02
104 #define WBSD_CLK_24M		0x03
105 
106 #define WBSD_DATA_WIDTH		0x01
107 
108 #define WBSD_DAT3_H		0x08
109 #define WBSD_FIFO_RESET		0x04
110 #define WBSD_SOFT_RESET		0x02
111 #define WBSD_INC_INDEX		0x01
112 
113 #define WBSD_DMA_SINGLE		0x02
114 #define WBSD_DMA_ENABLE		0x01
115 
116 #define WBSD_FIFOEN_EMPTY	0x20
117 #define WBSD_FIFOEN_FULL	0x10
118 #define WBSD_FIFO_THREMASK	0x0F
119 
120 #define WBSD_BLOCK_READ		0x80
121 #define WBSD_BLOCK_WRITE	0x40
122 #define WBSD_BUSY		0x20
123 #define WBSD_CARDTRAFFIC	0x04
124 #define WBSD_SENDCMD		0x02
125 #define WBSD_RECVRES		0x01
126 
127 #define WBSD_RSP_SHORT		0x00
128 #define WBSD_RSP_LONG		0x01
129 
130 #define WBSD_CRC_MASK		0x1F
131 #define WBSD_CRC_OK		0x05 /* S010E (00101) */
132 #define WBSD_CRC_FAIL		0x0B /* S101E (01011) */
133 
134 #define WBSD_DMA_SIZE		65536
135 
136 struct wbsd_host
137 {
138 	struct mmc_host*	mmc;		/* MMC structure */
139 
140 	spinlock_t		lock;		/* Mutex */
141 
142 	int			flags;		/* Driver states */
143 
144 #define WBSD_FCARD_PRESENT	(1<<0)		/* Card is present */
145 #define WBSD_FIGNORE_DETECT	(1<<1)		/* Ignore card detection */
146 
147 	struct mmc_request*	mrq;		/* Current request */
148 
149 	u8			isr;		/* Accumulated ISR */
150 
151 	struct scatterlist*	cur_sg;		/* Current SG entry */
152 	unsigned int		num_sg;		/* Number of entries left */
153 
154 	unsigned int		offset;		/* Offset into current entry */
155 	unsigned int		remain;		/* Data left in curren entry */
156 
157 	char*			dma_buffer;	/* ISA DMA buffer */
158 	dma_addr_t		dma_addr;	/* Physical address for same */
159 
160 	int			firsterr;	/* See fifo functions */
161 
162 	u8			clk;		/* Current clock speed */
163 	unsigned char		bus_width;	/* Current bus width */
164 
165 	int			config;		/* Config port */
166 	u8			unlock_code;	/* Code to unlock config */
167 
168 	int			chip_id;	/* ID of controller */
169 
170 	int			base;		/* I/O port base */
171 	int			irq;		/* Interrupt */
172 	int			dma;		/* DMA channel */
173 
174 	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
175 	struct tasklet_struct	fifo_tasklet;
176 	struct tasklet_struct	crc_tasklet;
177 	struct tasklet_struct	timeout_tasklet;
178 	struct tasklet_struct	finish_tasklet;
179 
180 	struct timer_list	ignore_timer;	/* Ignore detection timer */
181 };
182