Searched refs:VT1724_SPDIF_MASTER (Results 1 – 4 of 4) sorted by relevance
130 #define VT1724_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ macro
852 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); in qtet_set_rate()989 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); in qtet_init()
530 outb(val | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); in juli_set_rate()
89 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0; in stdclock_is_spdif_master()1869 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE)); in stdclock_set_spdif_clock()