Searched refs:VPU_MAFBC_S0_ENABLE (Results 1 – 2 of 2) sorted by relevance
321 meson_rdma_writel_sync(priv, VPU_MAFBC_S0_ENABLE, in meson_g12a_afbcd_enable()335 writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, 0, in meson_g12a_afbcd_disable()
1751 #define VPU_MAFBC_S0_ENABLE BIT(0) macro