Searched refs:VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE (Results 1 – 3 of 3) sorted by relevance
283 #define VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE 0x000000f7 /* 247 */ macro
861 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, in sdma_v2_4_sw_init()
1139 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, in sdma_v3_0_sw_init()