Searched refs:VF610_CLK_PLL4_MAIN_DIV (Results 1 – 2 of 2) sorted by relevance
39 #define VF610_CLK_PLL4_MAIN_DIV 30 macro
278 …clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0,… in vf610_clocks_init()