Searched refs:VCLK0_FB_DIV (Results 1 – 3 of 3) sorted by relevance
332 tmp = VCLK0_FB_DIV + par->clk_wr_offset; in aty_set_pll_ct()388 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; in aty_get_pll_ct()
3106 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()
802 #define VCLK0_FB_DIV 0x07 macro