1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*  D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 /*
4     Copyright (c) 2001, 2002 by D-Link Corporation
5     Written by Edward Peng.<edward_peng@dlink.com.tw>
6     Created 03-May-2001, base on Linux' sundance.c.
7 
8 */
9 
10 #ifndef __DL2K_H__
11 #define __DL2K_H__
12 
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/string.h>
16 #include <linux/timer.h>
17 #include <linux/errno.h>
18 #include <linux/ioport.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/crc32.h>
26 #include <linux/ethtool.h>
27 #include <linux/mii.h>
28 #include <linux/bitops.h>
29 #include <asm/processor.h>	/* Processor type for cache alignment. */
30 #include <asm/io.h>
31 #include <linux/uaccess.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/time.h>
35 #define TX_RING_SIZE	256
36 #define TX_QUEUE_LEN	(TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
37 #define RX_RING_SIZE 	256
38 #define TX_TOTAL_SIZE	TX_RING_SIZE*sizeof(struct netdev_desc)
39 #define RX_TOTAL_SIZE	RX_RING_SIZE*sizeof(struct netdev_desc)
40 
41 /* Offsets to the device registers.
42    Unlike software-only systems, device drivers interact with complex hardware.
43    It's not useful to define symbolic names for every register bit in the
44    device.  The name can only partially document the semantics and make
45    the driver longer and more difficult to read.
46    In general, only the important configuration values or bits changed
47    multiple times should be defined symbolically.
48 */
49 enum dl2x_offsets {
50 	/* I/O register offsets */
51 	DMACtrl = 0x00,
52 	RxDMAStatus = 0x08,
53 	TFDListPtr0 = 0x10,
54 	TFDListPtr1 = 0x14,
55 	TxDMABurstThresh = 0x18,
56 	TxDMAUrgentThresh = 0x19,
57 	TxDMAPollPeriod = 0x1a,
58 	RFDListPtr0 = 0x1c,
59 	RFDListPtr1 = 0x20,
60 	RxDMABurstThresh = 0x24,
61 	RxDMAUrgentThresh = 0x25,
62 	RxDMAPollPeriod = 0x26,
63 	RxDMAIntCtrl = 0x28,
64 	DebugCtrl = 0x2c,
65 	ASICCtrl = 0x30,
66 	FifoCtrl = 0x38,
67 	RxEarlyThresh = 0x3a,
68 	FlowOffThresh = 0x3c,
69 	FlowOnThresh = 0x3e,
70 	TxStartThresh = 0x44,
71 	EepromData = 0x48,
72 	EepromCtrl = 0x4a,
73 	ExpromAddr = 0x4c,
74 	Exprodata = 0x50,
75 	WakeEvent = 0x51,
76 	CountDown = 0x54,
77 	IntStatusAck = 0x5a,
78 	IntEnable = 0x5c,
79 	IntStatus = 0x5e,
80 	TxStatus = 0x60,
81 	MACCtrl = 0x6c,
82 	VLANTag = 0x70,
83 	PhyCtrl = 0x76,
84 	StationAddr0 = 0x78,
85 	StationAddr1 = 0x7a,
86 	StationAddr2 = 0x7c,
87 	VLANId = 0x80,
88 	MaxFrameSize = 0x86,
89 	ReceiveMode = 0x88,
90 	HashTable0 = 0x8c,
91 	HashTable1 = 0x90,
92 	RmonStatMask = 0x98,
93 	StatMask = 0x9c,
94 	RxJumboFrames = 0xbc,
95 	TCPCheckSumErrors = 0xc0,
96 	IPCheckSumErrors = 0xc2,
97 	UDPCheckSumErrors = 0xc4,
98 	TxJumboFrames = 0xf4,
99 	/* Ethernet MIB statistic register offsets */
100 	OctetRcvOk = 0xa8,
101 	McstOctetRcvOk = 0xac,
102 	BcstOctetRcvOk = 0xb0,
103 	FramesRcvOk = 0xb4,
104 	McstFramesRcvdOk = 0xb8,
105 	BcstFramesRcvdOk = 0xbe,
106 	MacControlFramesRcvd = 0xc6,
107 	FrameTooLongErrors = 0xc8,
108 	InRangeLengthErrors = 0xca,
109 	FramesCheckSeqErrors = 0xcc,
110 	FramesLostRxErrors = 0xce,
111 	OctetXmtOk = 0xd0,
112 	McstOctetXmtOk = 0xd4,
113 	BcstOctetXmtOk = 0xd8,
114 	FramesXmtOk = 0xdc,
115 	McstFramesXmtdOk = 0xe0,
116 	FramesWDeferredXmt = 0xe4,
117 	LateCollisions = 0xe8,
118 	MultiColFrames = 0xec,
119 	SingleColFrames = 0xf0,
120 	BcstFramesXmtdOk = 0xf6,
121 	CarrierSenseErrors = 0xf8,
122 	MacControlFramesXmtd = 0xfa,
123 	FramesAbortXSColls = 0xfc,
124 	FramesWEXDeferal = 0xfe,
125 	/* RMON statistic register offsets */
126 	EtherStatsCollisions = 0x100,
127 	EtherStatsOctetsTransmit = 0x104,
128 	EtherStatsPktsTransmit = 0x108,
129 	EtherStatsPkts64OctetTransmit = 0x10c,
130 	EtherStats65to127OctetsTransmit = 0x110,
131 	EtherStatsPkts128to255OctetsTransmit = 0x114,
132 	EtherStatsPkts256to511OctetsTransmit = 0x118,
133 	EtherStatsPkts512to1023OctetsTransmit = 0x11c,
134 	EtherStatsPkts1024to1518OctetsTransmit = 0x120,
135 	EtherStatsCRCAlignErrors = 0x124,
136 	EtherStatsUndersizePkts = 0x128,
137 	EtherStatsFragments = 0x12c,
138 	EtherStatsJabbers = 0x130,
139 	EtherStatsOctets = 0x134,
140 	EtherStatsPkts = 0x138,
141 	EtherStats64Octets = 0x13c,
142 	EtherStatsPkts65to127Octets = 0x140,
143 	EtherStatsPkts128to255Octets = 0x144,
144 	EtherStatsPkts256to511Octets = 0x148,
145 	EtherStatsPkts512to1023Octets = 0x14c,
146 	EtherStatsPkts1024to1518Octets = 0x150,
147 };
148 
149 /* Bits in the interrupt status/mask registers. */
150 enum IntStatus_bits {
151 	InterruptStatus = 0x0001,
152 	HostError = 0x0002,
153 	MACCtrlFrame = 0x0008,
154 	TxComplete = 0x0004,
155 	RxComplete = 0x0010,
156 	RxEarly = 0x0020,
157 	IntRequested = 0x0040,
158 	UpdateStats = 0x0080,
159 	LinkEvent = 0x0100,
160 	TxDMAComplete = 0x0200,
161 	RxDMAComplete = 0x0400,
162 	RFDListEnd = 0x0800,
163 	RxDMAPriority = 0x1000,
164 };
165 
166 /* Bits in the ReceiveMode register. */
167 enum ReceiveMode_bits {
168 	ReceiveUnicast = 0x0001,
169 	ReceiveMulticast = 0x0002,
170 	ReceiveBroadcast = 0x0004,
171 	ReceiveAllFrames = 0x0008,
172 	ReceiveMulticastHash = 0x0010,
173 	ReceiveIPMulticast = 0x0020,
174 	ReceiveVLANMatch = 0x0100,
175 	ReceiveVLANHash = 0x0200,
176 };
177 /* Bits in MACCtrl. */
178 enum MACCtrl_bits {
179 	DuplexSelect = 0x20,
180 	TxFlowControlEnable = 0x80,
181 	RxFlowControlEnable = 0x0100,
182 	RcvFCS = 0x200,
183 	AutoVLANtagging = 0x1000,
184 	AutoVLANuntagging = 0x2000,
185 	StatsEnable = 0x00200000,
186 	StatsDisable = 0x00400000,
187 	StatsEnabled = 0x00800000,
188 	TxEnable = 0x01000000,
189 	TxDisable = 0x02000000,
190 	TxEnabled = 0x04000000,
191 	RxEnable = 0x08000000,
192 	RxDisable = 0x10000000,
193 	RxEnabled = 0x20000000,
194 };
195 
196 enum ASICCtrl_LoWord_bits {
197 	PhyMedia = 0x0080,
198 };
199 
200 enum ASICCtrl_HiWord_bits {
201 	GlobalReset = 0x0001,
202 	RxReset = 0x0002,
203 	TxReset = 0x0004,
204 	DMAReset = 0x0008,
205 	FIFOReset = 0x0010,
206 	NetworkReset = 0x0020,
207 	HostReset = 0x0040,
208 	ResetBusy = 0x0400,
209 };
210 
211 #define IPG_AC_LED_MODE		BIT(14)
212 #define IPG_AC_LED_SPEED	BIT(27)
213 #define IPG_AC_LED_MODE_BIT_1	BIT(29)
214 
215 /* Transmit Frame Control bits */
216 enum TFC_bits {
217 	DwordAlign = 0x00000000,
218 	WordAlignDisable = 0x00030000,
219 	WordAlign = 0x00020000,
220 	TCPChecksumEnable = 0x00040000,
221 	UDPChecksumEnable = 0x00080000,
222 	IPChecksumEnable = 0x00100000,
223 	FCSAppendDisable = 0x00200000,
224 	TxIndicate = 0x00400000,
225 	TxDMAIndicate = 0x00800000,
226 	FragCountShift = 24,
227 	VLANTagInsert = 0x0000000010000000,
228 	TFDDone = 0x80000000,
229 	VIDShift = 32,
230 	UsePriorityShift = 48,
231 };
232 
233 /* Receive Frames Status bits */
234 enum RFS_bits {
235 	RxFIFOOverrun = 0x00010000,
236 	RxRuntFrame = 0x00020000,
237 	RxAlignmentError = 0x00040000,
238 	RxFCSError = 0x00080000,
239 	RxOverSizedFrame = 0x00100000,
240 	RxLengthError = 0x00200000,
241 	VLANDetected = 0x00400000,
242 	TCPDetected = 0x00800000,
243 	TCPError = 0x01000000,
244 	UDPDetected = 0x02000000,
245 	UDPError = 0x04000000,
246 	IPDetected = 0x08000000,
247 	IPError = 0x10000000,
248 	FrameStart = 0x20000000,
249 	FrameEnd = 0x40000000,
250 	RFDDone = 0x80000000,
251 	TCIShift = 32,
252 	RFS_Errors = 0x003f0000,
253 };
254 
255 #define MII_RESET_TIME_OUT		10000
256 /* MII register */
257 enum _mii_reg {
258 	MII_PHY_SCR = 16,
259 };
260 
261 /* PCS register */
262 enum _pcs_reg {
263 	PCS_BMCR = 0,
264 	PCS_BMSR = 1,
265 	PCS_ANAR = 4,
266 	PCS_ANLPAR = 5,
267 	PCS_ANER = 6,
268 	PCS_ANNPT = 7,
269 	PCS_ANLPRNP = 8,
270 	PCS_ESR = 15,
271 };
272 
273 /* IEEE Extened Status Register */
274 enum _mii_esr {
275 	MII_ESR_1000BX_FD = 0x8000,
276 	MII_ESR_1000BX_HD = 0x4000,
277 	MII_ESR_1000BT_FD = 0x2000,
278 	MII_ESR_1000BT_HD = 0x1000,
279 };
280 /* PHY Specific Control Register */
281 #if 0
282 typedef union t_MII_PHY_SCR {
283 	u16 image;
284 	struct {
285 		u16 disable_jabber:1;	// bit 0
286 		u16 polarity_reversal:1;	// bit 1
287 		u16 SEQ_test:1;	// bit 2
288 		u16 _bit_3:1;	// bit 3
289 		u16 disable_CLK125:1;	// bit 4
290 		u16 mdi_crossover_mode:2;	// bit 6:5
291 		u16 enable_ext_dist:1;	// bit 7
292 		u16 _bit_8_9:2;	// bit 9:8
293 		u16 force_link:1;	// bit 10
294 		u16 assert_CRS:1;	// bit 11
295 		u16 rcv_fifo_depth:2;	// bit 13:12
296 		u16 xmit_fifo_depth:2;	// bit 15:14
297 	} bits;
298 } PHY_SCR_t, *PPHY_SCR_t;
299 #endif
300 
301 typedef enum t_MII_ADMIN_STATUS {
302 	adm_reset,
303 	adm_operational,
304 	adm_loopback,
305 	adm_power_down,
306 	adm_isolate
307 } MII_ADMIN_t, *PMII_ADMIN_t;
308 
309 /* Physical Coding Sublayer Management (PCS) */
310 /* PCS control and status registers bitmap as the same as MII */
311 /* PCS Extended Status register bitmap as the same as MII */
312 /* PCS ANAR */
313 enum _pcs_anar {
314 	PCS_ANAR_NEXT_PAGE = 0x8000,
315 	PCS_ANAR_REMOTE_FAULT = 0x3000,
316 	PCS_ANAR_ASYMMETRIC = 0x0100,
317 	PCS_ANAR_PAUSE = 0x0080,
318 	PCS_ANAR_HALF_DUPLEX = 0x0040,
319 	PCS_ANAR_FULL_DUPLEX = 0x0020,
320 };
321 /* PCS ANLPAR */
322 enum _pcs_anlpar {
323 	PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
324 	PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
325 	PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
326 	PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
327 	PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
328 	PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
329 };
330 
331 typedef struct t_SROM {
332 	u16 config_param;	/* 0x00 */
333 	u16 asic_ctrl;		/* 0x02 */
334 	u16 sub_vendor_id;	/* 0x04 */
335 	u16 sub_system_id;	/* 0x06 */
336 	u16 pci_base_1;		/* 0x08 (IP1000A only) */
337 	u16 pci_base_2;		/* 0x0a (IP1000A only) */
338 	u16 led_mode;		/* 0x0c (IP1000A only) */
339 	u16 reserved1[9];	/* 0x0e-0x1f */
340 	u8 mac_addr[6];		/* 0x20-0x25 */
341 	u8 reserved2[10];	/* 0x26-0x2f */
342 	u8 sib[204];		/* 0x30-0xfb */
343 	u32 crc;		/* 0xfc-0xff */
344 } SROM_t, *PSROM_t;
345 
346 /* Ioctl custom data */
347 struct ioctl_data {
348 	char signature[10];
349 	int cmd;
350 	int len;
351 	char *data;
352 };
353 
354 /* The Rx and Tx buffer descriptors. */
355 struct netdev_desc {
356 	__le64 next_desc;
357 	__le64 status;
358 	__le64 fraginfo;
359 };
360 
361 #define PRIV_ALIGN	15	/* Required alignment mask */
362 /* Use  __attribute__((aligned (L1_CACHE_BYTES)))  to maintain alignment
363    within the structure. */
364 struct netdev_private {
365 	/* Descriptor rings first for alignment. */
366 	struct netdev_desc *rx_ring;
367 	struct netdev_desc *tx_ring;
368 	struct sk_buff *rx_skbuff[RX_RING_SIZE];
369 	struct sk_buff *tx_skbuff[TX_RING_SIZE];
370 	dma_addr_t tx_ring_dma;
371 	dma_addr_t rx_ring_dma;
372 	struct pci_dev *pdev;
373 	void __iomem *ioaddr;
374 	void __iomem *eeprom_addr;
375 	spinlock_t tx_lock;
376 	spinlock_t rx_lock;
377 	unsigned int rx_buf_sz;		/* Based on MTU+slack. */
378 	unsigned int speed;		/* Operating speed */
379 	unsigned int vlan;		/* VLAN Id */
380 	unsigned int chip_id;		/* PCI table chip id */
381 	unsigned int rx_coalesce; 	/* Maximum frames each RxDMAComplete intr */
382 	unsigned int rx_timeout; 	/* Wait time between RxDMAComplete intr */
383 	unsigned int tx_coalesce;	/* Maximum frames each tx interrupt */
384 	unsigned int full_duplex:1;	/* Full-duplex operation requested. */
385 	unsigned int an_enable:2;	/* Auto-Negotiated Enable */
386 	unsigned int jumbo:1;		/* Jumbo frame enable */
387 	unsigned int coalesce:1;	/* Rx coalescing enable */
388 	unsigned int tx_flow:1;		/* Tx flow control enable */
389 	unsigned int rx_flow:1;		/* Rx flow control enable */
390 	unsigned int phy_media:1;	/* 1: fiber, 0: copper */
391 	unsigned int link_status:1;	/* Current link status */
392 	struct netdev_desc *last_tx;	/* Last Tx descriptor used. */
393 	unsigned long cur_rx, old_rx;	/* Producer/consumer ring indices */
394 	unsigned long cur_tx, old_tx;
395 	struct timer_list timer;
396 	int wake_polarity;
397 	char name[256];		/* net device description */
398 	u8 duplex_polarity;
399 	u16 mcast_filter[4];
400 	u16 advertising;	/* NWay media advertisement */
401 	u16 negotiate;		/* Negotiated media */
402 	int phy_addr;		/* PHY addresses. */
403 	u16 led_mode;		/* LED mode read from EEPROM (IP1000A only) */
404 };
405 
406 /* The station address location in the EEPROM. */
407 /* The struct pci_device_id consist of:
408         vendor, device          Vendor and device ID to match (or PCI_ANY_ID)
409         subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
410         class                   Device class to match. The class_mask tells which bits
411         class_mask              of the class are honored during the comparison.
412         driver_data             Data private to the driver.
413 */
414 #define CHIP_IP1000A	1
415 
416 static const struct pci_device_id rio_pci_tbl[] = {
417 	{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
418 	{0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
419 	{ PCI_VDEVICE(SUNDANCE,	0x1023), CHIP_IP1000A },
420 	{ PCI_VDEVICE(SUNDANCE,	0x2021), CHIP_IP1000A },
421 	{ PCI_VDEVICE(DLINK,	0x9021), CHIP_IP1000A },
422 	{ PCI_VDEVICE(DLINK,	0x4020), CHIP_IP1000A },
423 	{ }
424 };
425 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
426 #define TX_TIMEOUT  (4*HZ)
427 #define PACKET_SIZE		1536
428 #define MAX_JUMBO		8000
429 #define RIO_IO_SIZE             340
430 #define DEFAULT_RXC		5
431 #define DEFAULT_RXT		750
432 #define DEFAULT_TXC		1
433 #define MAX_TXC			8
434 #endif				/* __DL2K_H__ */
435