Searched refs:TSUNAMI_cchip (Results 1 – 3 of 3) sorted by relevance
/linux-5.19.10/arch/alpha/kernel/ |
D | core_tsunami.c | 227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write() 231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write() 232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write() 233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write() 387 tmp = (unsigned long)(TSUNAMI_cchip - 1); in tsunami_init_arch() 396 printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr); in tsunami_init_arch() 397 printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); in tsunami_init_arch() 398 printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr); in tsunami_init_arch() 399 printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr); in tsunami_init_arch() 400 printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); in tsunami_init_arch() [all …]
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D | sys_dp264.c | 49 register tsunami_cchip *cchip = TSUNAMI_cchip; in tsunami_update_irq_hw() 197 pld = TSUNAMI_cchip->dir0.csr; in dp264_device_interrupt()
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/linux-5.19.10/arch/alpha/include/asm/ |
D | core_tsunami.h | 89 #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL)) macro
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