Searched refs:TRCVMIDCCTLR0 (Results 1 – 3 of 3) sorted by relevance
73 CHECKREG(TRCVMIDCCTLR0, vmid_mask0); in etm4_cfg_map_reg_offset()
101 #define TRCVMIDCCTLR0 0x688 macro459 CASE_##op((val), TRCVMIDCCTLR0) \
464 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); in etm4_enable_hw()1662 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); in __etm4_cpu_save()1784 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); in __etm4_cpu_restore()