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Searched refs:TLBTEMP_BASE_1 (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/arch/xtensa/mm/
Dcache.c70 kvaddr = TLBTEMP_BASE_1 + in kmap_invalidate_coherent()
91 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr); in clear_user_highpage()
105 void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr, in copy_user_highpage()
157 virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); in flush_dcache_page()
160 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK); in flush_dcache_page()
199 unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK); in local_flush_cache_page()
232 tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); in update_mmu_cache()
234 tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK); in update_mmu_cache()
270 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); in copy_to_user_page()
286 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); in copy_to_user_page()
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Dhighmem.c57 BUILD_BUG_ON(PKMAP_BASE < TLBTEMP_BASE_1 + TLBTEMP_SIZE); in kmap_init()
Dmmu.c57 BUILD_BUG_ON(FIXADDR_START < TLBTEMP_BASE_1 + TLBTEMP_SIZE); in fixedrange_init()
/linux-5.19.10/Documentation/xtensa/
Dmmu.rst86 | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
129 | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
173 | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
/linux-5.19.10/arch/xtensa/include/asm/
Dpgtable.h71 #define TLBTEMP_BASE_1 (VMALLOC_START + 0x08000000) macro
72 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
/linux-5.19.10/arch/xtensa/kernel/
Dentry.S1753 movi a3, TLBTEMP_BASE_1