Searched refs:TEGRA_DIVIDER_ROUND_UP (Results 1 – 10 of 10) sorted by relevance
| /linux-5.19.10/drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 135 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
142 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
161 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
169 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
176 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
190 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
197 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
[all …]
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| D | clk-utils.c | 26 if (flags & TEGRA_DIVIDER_ROUND_UP) in div_frac_get()
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| D | clk-tegra20.c | 139 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
146 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
637 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
651 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
685 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
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| D | clk-tegra30.c | 161 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
167 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
174 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
820 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
829 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
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| D | clk-tegra-audio.c | 194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
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| D | clk-tegra210.c | 3073 TEGRA_DIVIDER_ROUND_UP, 183, 0,
3087 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
3162 TEGRA_DIVIDER_ROUND_UP, 0, NULL); in tegra210_periph_clk_init()
3167 TEGRA_DIVIDER_ROUND_UP, 0, NULL); in tegra210_periph_clk_init()
3208 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3281 TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3292 TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3349 TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3389 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
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| D | clk-sdmmc-mux.c | 124 if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP) in clk_sdmmc_mux_determine_rate()
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| D | clk-tegra114.c | 118 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
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| D | clk-tegra124.c | 99 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
1099 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
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| D | clk.h | 128 #define TEGRA_DIVIDER_ROUND_UP BIT(0) macro
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