Searched refs:TEGRA20_CLK_PLL_A_OUT0 (Results 1 – 14 of 14) sorted by relevance
| /linux-5.19.10/include/dt-bindings/clock/ |
| D | tegra20-car.h | 136 #define TEGRA20_CLK_PLL_A_OUT0 113 macro
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| /linux-5.19.10/drivers/clk/tegra/ |
| D | clk-tegra20.c | 435 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
690 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
1032 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
1033 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1034 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | tegra20-plutux.dts | 58 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-tec.dts | 67 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-medcom-wide.dts | 93 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-trimslice.dts | 461 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-paz00.dts | 666 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-ventana.dts | 718 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-harmony.dts | 757 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-colibri.dtsi | 743 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-seaboard.dts | 916 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20.dtsi | 404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
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| D | tegra20-asus-tf101.dts | 1193 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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| D | tegra20-acer-a500-picasso.dts | 1040 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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