1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
6 //
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
11
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
19 #include <linux/pm_runtime.h>
20
21 #include <sound/asoundef.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/soc.h>
24
25 #include "fsl_spdif.h"
26 #include "imx-pcm.h"
27
28 #define FSL_SPDIF_TXFIFO_WML 0x8
29 #define FSL_SPDIF_RXFIFO_WML 0x8
30
31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
35 INT_LOSS_LOCK | INT_DPLL_LOCKED)
36
37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
38
39 /* Index list for the values that has if (DPLL Locked) condition */
40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
41 #define SRPC_NODPLL_START1 0x5
42 #define SRPC_NODPLL_START2 0xc
43
44 #define DEFAULT_RXCLK_SRC 1
45
46 /**
47 * struct fsl_spdif_soc_data: soc specific data
48 *
49 * @imx: for imx platform
50 * @shared_root_clock: flag of sharing a clock source with others;
51 * so the driver shouldn't set root clock rate
52 * @raw_capture_mode: if raw capture mode support
53 * @cchannel_192b: if there are registers for 192bits C channel data
54 * @interrupts: interrupt number
55 * @tx_burst: tx maxburst size
56 * @rx_burst: rx maxburst size
57 * @tx_formats: tx supported data format
58 */
59 struct fsl_spdif_soc_data {
60 bool imx;
61 bool shared_root_clock;
62 bool raw_capture_mode;
63 bool cchannel_192b;
64 u32 interrupts;
65 u32 tx_burst;
66 u32 rx_burst;
67 u64 tx_formats;
68 };
69
70 /*
71 * SPDIF control structure
72 * Defines channel status, subcode and Q sub
73 */
74 struct spdif_mixer_control {
75 /* spinlock to access control data */
76 spinlock_t ctl_lock;
77
78 /* IEC958 channel tx status bit */
79 unsigned char ch_status[4];
80
81 /* User bits */
82 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
83
84 /* Q subcode part of user bits */
85 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
86
87 /* Buffer offset for U/Q */
88 u32 upos;
89 u32 qpos;
90
91 /* Ready buffer index of the two buffers */
92 u32 ready_buf;
93 };
94
95 /**
96 * struct fsl_spdif_priv - Freescale SPDIF private data
97 * @soc: SPDIF soc data
98 * @fsl_spdif_control: SPDIF control data
99 * @cpu_dai_drv: cpu dai driver
100 * @pdev: platform device pointer
101 * @regmap: regmap handler
102 * @dpll_locked: dpll lock flag
103 * @txrate: the best rates for playback
104 * @txclk_df: STC_TXCLK_DF dividers value for playback
105 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
106 * @txclk_src: STC_TXCLK_SRC values for playback
107 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
108 * @txclk: tx clock sources for playback
109 * @rxclk: rx clock sources for capture
110 * @coreclk: core clock for register access via DMA
111 * @sysclk: system clock for rx clock rate measurement
112 * @spbaclk: SPBA clock (optional, depending on SoC design)
113 * @dma_params_tx: DMA parameters for transmit channel
114 * @dma_params_rx: DMA parameters for receive channel
115 * @regcache_srpc: regcache for SRPC
116 * @bypass: status of bypass input to output
117 */
118 struct fsl_spdif_priv {
119 const struct fsl_spdif_soc_data *soc;
120 struct spdif_mixer_control fsl_spdif_control;
121 struct snd_soc_dai_driver cpu_dai_drv;
122 struct platform_device *pdev;
123 struct regmap *regmap;
124 bool dpll_locked;
125 u32 txrate[SPDIF_TXRATE_MAX];
126 u8 txclk_df[SPDIF_TXRATE_MAX];
127 u16 sysclk_df[SPDIF_TXRATE_MAX];
128 u8 txclk_src[SPDIF_TXRATE_MAX];
129 u8 rxclk_src;
130 struct clk *txclk[STC_TXCLK_SRC_MAX];
131 struct clk *rxclk;
132 struct clk *coreclk;
133 struct clk *sysclk;
134 struct clk *spbaclk;
135 struct snd_dmaengine_dai_dma_data dma_params_tx;
136 struct snd_dmaengine_dai_dma_data dma_params_rx;
137 /* regcache for SRPC */
138 u32 regcache_srpc;
139 bool bypass;
140 };
141
142 static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
143 .imx = false,
144 .shared_root_clock = false,
145 .raw_capture_mode = false,
146 .interrupts = 1,
147 .tx_burst = FSL_SPDIF_TXFIFO_WML,
148 .rx_burst = FSL_SPDIF_RXFIFO_WML,
149 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
150 };
151
152 static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
153 .imx = true,
154 .shared_root_clock = false,
155 .raw_capture_mode = false,
156 .interrupts = 1,
157 .tx_burst = FSL_SPDIF_TXFIFO_WML,
158 .rx_burst = FSL_SPDIF_RXFIFO_WML,
159 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
160 };
161
162 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
163 .imx = true,
164 .shared_root_clock = true,
165 .raw_capture_mode = false,
166 .interrupts = 1,
167 .tx_burst = FSL_SPDIF_TXFIFO_WML,
168 .rx_burst = FSL_SPDIF_RXFIFO_WML,
169 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
170
171 };
172
173 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {
174 .imx = true,
175 .shared_root_clock = true,
176 .raw_capture_mode = false,
177 .interrupts = 2,
178 .tx_burst = 2, /* Applied for EDMA */
179 .rx_burst = 2, /* Applied for EDMA */
180 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
181 };
182
183 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
184 .imx = true,
185 .shared_root_clock = false,
186 .raw_capture_mode = true,
187 .interrupts = 1,
188 .tx_burst = FSL_SPDIF_TXFIFO_WML,
189 .rx_burst = FSL_SPDIF_RXFIFO_WML,
190 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
191 };
192
193 static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
194 .imx = true,
195 .shared_root_clock = true,
196 .raw_capture_mode = false,
197 .interrupts = 1,
198 .tx_burst = 2, /* Applied for EDMA */
199 .rx_burst = 2, /* Applied for EDMA */
200 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
201 .cchannel_192b = true,
202 };
203
204 /* Check if clk is a root clock that does not share clock source with others */
fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv * spdif,int clk)205 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
206 {
207 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
208 }
209
210 /* DPLL locked and lock loss interrupt handler */
spdif_irq_dpll_lock(struct fsl_spdif_priv * spdif_priv)211 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
212 {
213 struct regmap *regmap = spdif_priv->regmap;
214 struct platform_device *pdev = spdif_priv->pdev;
215 u32 locked;
216
217 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
218 locked &= SRPC_DPLL_LOCKED;
219
220 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
221 locked ? "locked" : "loss lock");
222
223 spdif_priv->dpll_locked = locked ? true : false;
224 }
225
226 /* Receiver found illegal symbol interrupt handler */
spdif_irq_sym_error(struct fsl_spdif_priv * spdif_priv)227 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
228 {
229 struct regmap *regmap = spdif_priv->regmap;
230 struct platform_device *pdev = spdif_priv->pdev;
231
232 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
233
234 /* Clear illegal symbol if DPLL unlocked since no audio stream */
235 if (!spdif_priv->dpll_locked)
236 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
237 }
238
239 /* U/Q Channel receive register full */
spdif_irq_uqrx_full(struct fsl_spdif_priv * spdif_priv,char name)240 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
241 {
242 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
243 struct regmap *regmap = spdif_priv->regmap;
244 struct platform_device *pdev = spdif_priv->pdev;
245 u32 *pos, size, val, reg;
246
247 switch (name) {
248 case 'U':
249 pos = &ctrl->upos;
250 size = SPDIF_UBITS_SIZE;
251 reg = REG_SPDIF_SRU;
252 break;
253 case 'Q':
254 pos = &ctrl->qpos;
255 size = SPDIF_QSUB_SIZE;
256 reg = REG_SPDIF_SRQ;
257 break;
258 default:
259 dev_err(&pdev->dev, "unsupported channel name\n");
260 return;
261 }
262
263 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
264
265 if (*pos >= size * 2) {
266 *pos = 0;
267 } else if (unlikely((*pos % size) + 3 > size)) {
268 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
269 return;
270 }
271
272 regmap_read(regmap, reg, &val);
273 ctrl->subcode[*pos++] = val >> 16;
274 ctrl->subcode[*pos++] = val >> 8;
275 ctrl->subcode[*pos++] = val;
276 }
277
278 /* U/Q Channel sync found */
spdif_irq_uq_sync(struct fsl_spdif_priv * spdif_priv)279 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
280 {
281 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
282 struct platform_device *pdev = spdif_priv->pdev;
283
284 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
285
286 /* U/Q buffer reset */
287 if (ctrl->qpos == 0)
288 return;
289
290 /* Set ready to this buffer */
291 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
292 }
293
294 /* U/Q Channel framing error */
spdif_irq_uq_err(struct fsl_spdif_priv * spdif_priv)295 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
296 {
297 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
298 struct regmap *regmap = spdif_priv->regmap;
299 struct platform_device *pdev = spdif_priv->pdev;
300 u32 val;
301
302 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
303
304 /* Read U/Q data to clear the irq and do buffer reset */
305 regmap_read(regmap, REG_SPDIF_SRU, &val);
306 regmap_read(regmap, REG_SPDIF_SRQ, &val);
307
308 /* Drop this U/Q buffer */
309 ctrl->ready_buf = 0;
310 ctrl->upos = 0;
311 ctrl->qpos = 0;
312 }
313
314 /* Get spdif interrupt status and clear the interrupt */
spdif_intr_status_clear(struct fsl_spdif_priv * spdif_priv)315 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
316 {
317 struct regmap *regmap = spdif_priv->regmap;
318 u32 val, val2;
319
320 regmap_read(regmap, REG_SPDIF_SIS, &val);
321 regmap_read(regmap, REG_SPDIF_SIE, &val2);
322
323 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
324
325 return val;
326 }
327
spdif_isr(int irq,void * devid)328 static irqreturn_t spdif_isr(int irq, void *devid)
329 {
330 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
331 struct platform_device *pdev = spdif_priv->pdev;
332 u32 sis;
333
334 sis = spdif_intr_status_clear(spdif_priv);
335
336 if (sis & INT_DPLL_LOCKED)
337 spdif_irq_dpll_lock(spdif_priv);
338
339 if (sis & INT_TXFIFO_UNOV)
340 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
341
342 if (sis & INT_TXFIFO_RESYNC)
343 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
344
345 if (sis & INT_CNEW)
346 dev_dbg(&pdev->dev, "isr: cstatus new\n");
347
348 if (sis & INT_VAL_NOGOOD)
349 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
350
351 if (sis & INT_SYM_ERR)
352 spdif_irq_sym_error(spdif_priv);
353
354 if (sis & INT_BIT_ERR)
355 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
356
357 if (sis & INT_URX_FUL)
358 spdif_irq_uqrx_full(spdif_priv, 'U');
359
360 if (sis & INT_URX_OV)
361 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
362
363 if (sis & INT_QRX_FUL)
364 spdif_irq_uqrx_full(spdif_priv, 'Q');
365
366 if (sis & INT_QRX_OV)
367 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
368
369 if (sis & INT_UQ_SYNC)
370 spdif_irq_uq_sync(spdif_priv);
371
372 if (sis & INT_UQ_ERR)
373 spdif_irq_uq_err(spdif_priv);
374
375 if (sis & INT_RXFIFO_UNOV)
376 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
377
378 if (sis & INT_RXFIFO_RESYNC)
379 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
380
381 if (sis & INT_LOSS_LOCK)
382 spdif_irq_dpll_lock(spdif_priv);
383
384 /* FIXME: Write Tx FIFO to clear TxEm */
385 if (sis & INT_TX_EM)
386 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
387
388 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
389 if (sis & INT_RXFIFO_FUL)
390 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
391
392 return IRQ_HANDLED;
393 }
394
spdif_softreset(struct fsl_spdif_priv * spdif_priv)395 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
396 {
397 struct regmap *regmap = spdif_priv->regmap;
398 u32 val, cycle = 1000;
399
400 regcache_cache_bypass(regmap, true);
401
402 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
403
404 /*
405 * RESET bit would be cleared after finishing its reset procedure,
406 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
407 */
408 do {
409 regmap_read(regmap, REG_SPDIF_SCR, &val);
410 } while ((val & SCR_SOFT_RESET) && cycle--);
411
412 regcache_cache_bypass(regmap, false);
413 regcache_mark_dirty(regmap);
414 regcache_sync(regmap);
415
416 if (cycle)
417 return 0;
418 else
419 return -EBUSY;
420 }
421
spdif_set_cstatus(struct spdif_mixer_control * ctrl,u8 mask,u8 cstatus)422 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
423 u8 mask, u8 cstatus)
424 {
425 ctrl->ch_status[3] &= ~mask;
426 ctrl->ch_status[3] |= cstatus & mask;
427 }
428
spdif_write_channel_status(struct fsl_spdif_priv * spdif_priv)429 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
430 {
431 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
432 struct regmap *regmap = spdif_priv->regmap;
433 struct platform_device *pdev = spdif_priv->pdev;
434 u32 ch_status;
435
436 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
437 (bitrev8(ctrl->ch_status[1]) << 8) |
438 bitrev8(ctrl->ch_status[2]);
439 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
440
441 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
442
443 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
444 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
445
446 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
447
448 if (spdif_priv->soc->cchannel_192b) {
449 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
450 (bitrev8(ctrl->ch_status[1]) << 16) |
451 (bitrev8(ctrl->ch_status[2]) << 8) |
452 bitrev8(ctrl->ch_status[3]);
453
454 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);
455
456 /*
457 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
458 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
459 * then can get correct result with HDMI analyzer capture.
460 * There is a hardware bug here.
461 */
462 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
463 }
464 }
465
466 /* Set SPDIF PhaseConfig register for rx clock */
spdif_set_rx_clksrc(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel,int dpll_locked)467 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
468 enum spdif_gainsel gainsel, int dpll_locked)
469 {
470 struct regmap *regmap = spdif_priv->regmap;
471 u8 clksrc = spdif_priv->rxclk_src;
472
473 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
474 return -EINVAL;
475
476 regmap_update_bits(regmap, REG_SPDIF_SRPC,
477 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
478 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
479
480 return 0;
481 }
482
spdif_set_sample_rate(struct snd_pcm_substream * substream,int sample_rate)483 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
484 int sample_rate)
485 {
486 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
487 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
488 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
489 struct regmap *regmap = spdif_priv->regmap;
490 struct platform_device *pdev = spdif_priv->pdev;
491 unsigned long csfs = 0;
492 u32 stc, mask, rate;
493 u16 sysclk_df;
494 u8 clk, txclk_df;
495 int ret;
496
497 switch (sample_rate) {
498 case 32000:
499 rate = SPDIF_TXRATE_32000;
500 csfs = IEC958_AES3_CON_FS_32000;
501 break;
502 case 44100:
503 rate = SPDIF_TXRATE_44100;
504 csfs = IEC958_AES3_CON_FS_44100;
505 break;
506 case 48000:
507 rate = SPDIF_TXRATE_48000;
508 csfs = IEC958_AES3_CON_FS_48000;
509 break;
510 case 88200:
511 rate = SPDIF_TXRATE_88200;
512 csfs = IEC958_AES3_CON_FS_88200;
513 break;
514 case 96000:
515 rate = SPDIF_TXRATE_96000;
516 csfs = IEC958_AES3_CON_FS_96000;
517 break;
518 case 176400:
519 rate = SPDIF_TXRATE_176400;
520 csfs = IEC958_AES3_CON_FS_176400;
521 break;
522 case 192000:
523 rate = SPDIF_TXRATE_192000;
524 csfs = IEC958_AES3_CON_FS_192000;
525 break;
526 default:
527 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
528 return -EINVAL;
529 }
530
531 clk = spdif_priv->txclk_src[rate];
532 if (clk >= STC_TXCLK_SRC_MAX) {
533 dev_err(&pdev->dev, "tx clock source is out of range\n");
534 return -EINVAL;
535 }
536
537 txclk_df = spdif_priv->txclk_df[rate];
538 if (txclk_df == 0) {
539 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
540 return -EINVAL;
541 }
542
543 sysclk_df = spdif_priv->sysclk_df[rate];
544
545 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
546 goto clk_set_bypass;
547
548 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
549 ret = clk_set_rate(spdif_priv->txclk[clk],
550 64 * sample_rate * txclk_df);
551 if (ret) {
552 dev_err(&pdev->dev, "failed to set tx clock rate\n");
553 return ret;
554 }
555
556 clk_set_bypass:
557 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
558 (64 * sample_rate * txclk_df * sysclk_df));
559 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
560 clk_get_rate(spdif_priv->txclk[clk]));
561
562 /* set fs field in consumer channel status */
563 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
564
565 /* select clock source and divisor */
566 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
567 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
568 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
569 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
570 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
571
572 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
573 spdif_priv->txrate[rate], sample_rate);
574
575 return 0;
576 }
577
fsl_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)578 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
579 struct snd_soc_dai *cpu_dai)
580 {
581 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
582 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
583 struct platform_device *pdev = spdif_priv->pdev;
584 struct regmap *regmap = spdif_priv->regmap;
585 u32 scr, mask;
586 int ret;
587
588 /* Reset module and interrupts only for first initialization */
589 if (!snd_soc_dai_active(cpu_dai)) {
590 ret = spdif_softreset(spdif_priv);
591 if (ret) {
592 dev_err(&pdev->dev, "failed to soft reset\n");
593 return ret;
594 }
595
596 /* Disable all the interrupts */
597 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
598 }
599
600 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
601 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
602 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
603 SCR_TXFIFO_FSEL_IF8;
604 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
605 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
606 SCR_TXFIFO_FSEL_MASK;
607 } else {
608 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
609 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
610 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
611 }
612 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
613
614 /* Power up SPDIF module */
615 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
616
617 return 0;
618 }
619
fsl_spdif_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)620 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
621 struct snd_soc_dai *cpu_dai)
622 {
623 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
624 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
625 struct regmap *regmap = spdif_priv->regmap;
626 u32 scr, mask;
627
628 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
629 scr = 0;
630 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
631 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
632 SCR_TXFIFO_FSEL_MASK;
633 /* Disable TX clock */
634 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
635 } else {
636 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
637 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
638 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
639 }
640 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
641
642 /* Power down SPDIF module only if tx&rx are both inactive */
643 if (!snd_soc_dai_active(cpu_dai)) {
644 spdif_intr_status_clear(spdif_priv);
645 regmap_update_bits(regmap, REG_SPDIF_SCR,
646 SCR_LOW_POWER, SCR_LOW_POWER);
647 }
648 }
649
fsl_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)650 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
651 struct snd_pcm_hw_params *params,
652 struct snd_soc_dai *dai)
653 {
654 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
655 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
656 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
657 struct platform_device *pdev = spdif_priv->pdev;
658 u32 sample_rate = params_rate(params);
659 int ret = 0;
660
661 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
662 ret = spdif_set_sample_rate(substream, sample_rate);
663 if (ret) {
664 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
665 __func__, sample_rate);
666 return ret;
667 }
668 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
669 IEC958_AES3_CON_CLOCK_1000PPM);
670 spdif_write_channel_status(spdif_priv);
671 } else {
672 /* Setup rx clock source */
673 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
674 }
675
676 return ret;
677 }
678
fsl_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)679 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
680 int cmd, struct snd_soc_dai *dai)
681 {
682 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
683 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
684 struct regmap *regmap = spdif_priv->regmap;
685 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
686 u32 intr = SIE_INTR_FOR(tx);
687 u32 dmaen = SCR_DMA_xX_EN(tx);
688
689 switch (cmd) {
690 case SNDRV_PCM_TRIGGER_START:
691 case SNDRV_PCM_TRIGGER_RESUME:
692 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
693 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
694 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
695 break;
696 case SNDRV_PCM_TRIGGER_STOP:
697 case SNDRV_PCM_TRIGGER_SUSPEND:
698 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
699 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
700 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
701 break;
702 default:
703 return -EINVAL;
704 }
705
706 return 0;
707 }
708
709 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
710 .startup = fsl_spdif_startup,
711 .hw_params = fsl_spdif_hw_params,
712 .trigger = fsl_spdif_trigger,
713 .shutdown = fsl_spdif_shutdown,
714 };
715
716
717 /*
718 * FSL SPDIF IEC958 controller(mixer) functions
719 *
720 * Channel status get/put control
721 * User bit value get/put control
722 * Valid bit value get control
723 * DPLL lock status get control
724 * User bit sync mode selection control
725 */
726
fsl_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)727 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_info *uinfo)
729 {
730 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
731 uinfo->count = 1;
732
733 return 0;
734 }
735
fsl_spdif_pb_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)736 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
737 struct snd_ctl_elem_value *uvalue)
738 {
739 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
740 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
741 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
742
743 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
744 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
745 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
746 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
747
748 return 0;
749 }
750
fsl_spdif_pb_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)751 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
752 struct snd_ctl_elem_value *uvalue)
753 {
754 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
755 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
756 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
757
758 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
759 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
760 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
761 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
762
763 spdif_write_channel_status(spdif_priv);
764
765 return 0;
766 }
767
768 /* Get channel status from SPDIF_RX_CCHAN register */
fsl_spdif_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)769 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
770 struct snd_ctl_elem_value *ucontrol)
771 {
772 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
773 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
774 struct regmap *regmap = spdif_priv->regmap;
775 u32 cstatus, val;
776
777 regmap_read(regmap, REG_SPDIF_SIS, &val);
778 if (!(val & INT_CNEW))
779 return -EAGAIN;
780
781 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
782 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
783 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
784 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
785
786 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
787 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
788 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
789 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
790
791 /* Clear intr */
792 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
793
794 return 0;
795 }
796
797 /*
798 * Get User bits (subcode) from chip value which readed out
799 * in UChannel register.
800 */
fsl_spdif_subcode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)801 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
802 struct snd_ctl_elem_value *ucontrol)
803 {
804 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
805 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
806 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
807 unsigned long flags;
808 int ret = -EAGAIN;
809
810 spin_lock_irqsave(&ctrl->ctl_lock, flags);
811 if (ctrl->ready_buf) {
812 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
813 memcpy(&ucontrol->value.iec958.subcode[0],
814 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
815 ret = 0;
816 }
817 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
818
819 return ret;
820 }
821
822 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
fsl_spdif_qinfo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)823 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
824 struct snd_ctl_elem_info *uinfo)
825 {
826 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
827 uinfo->count = SPDIF_QSUB_SIZE;
828
829 return 0;
830 }
831
832 /* Get Q subcode from chip value which readed out in QChannel register */
fsl_spdif_qget(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)833 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
834 struct snd_ctl_elem_value *ucontrol)
835 {
836 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
837 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
838 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
839 unsigned long flags;
840 int ret = -EAGAIN;
841
842 spin_lock_irqsave(&ctrl->ctl_lock, flags);
843 if (ctrl->ready_buf) {
844 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
845 memcpy(&ucontrol->value.bytes.data[0],
846 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
847 ret = 0;
848 }
849 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
850
851 return ret;
852 }
853
854 /* Get valid good bit from interrupt status register */
fsl_spdif_rx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)855 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
856 struct snd_ctl_elem_value *ucontrol)
857 {
858 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
859 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
860 struct regmap *regmap = spdif_priv->regmap;
861 u32 val;
862
863 regmap_read(regmap, REG_SPDIF_SIS, &val);
864 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
865 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
866
867 return 0;
868 }
869
fsl_spdif_tx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)870 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
871 struct snd_ctl_elem_value *ucontrol)
872 {
873 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
874 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
875 struct regmap *regmap = spdif_priv->regmap;
876 u32 val;
877
878 regmap_read(regmap, REG_SPDIF_SCR, &val);
879 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
880 val = 1 - val;
881 ucontrol->value.integer.value[0] = val;
882
883 return 0;
884 }
885
fsl_spdif_tx_vbit_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)886 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
887 struct snd_ctl_elem_value *ucontrol)
888 {
889 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
890 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
891 struct regmap *regmap = spdif_priv->regmap;
892 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
893
894 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
895
896 return 0;
897 }
898
fsl_spdif_rx_rcm_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)899 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol,
900 struct snd_ctl_elem_value *ucontrol)
901 {
902 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
903 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
904 struct regmap *regmap = spdif_priv->regmap;
905 u32 val;
906
907 regmap_read(regmap, REG_SPDIF_SCR, &val);
908 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0;
909 ucontrol->value.integer.value[0] = val;
910
911 return 0;
912 }
913
fsl_spdif_rx_rcm_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)914 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol,
915 struct snd_ctl_elem_value *ucontrol)
916 {
917 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
918 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
919 struct regmap *regmap = spdif_priv->regmap;
920 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0);
921
922 if (val)
923 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE;
924 else
925 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE;
926
927 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val);
928
929 return 0;
930 }
931
fsl_spdif_bypass_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)932 static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol,
933 struct snd_ctl_elem_value *ucontrol)
934 {
935 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
936 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
937
938 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0;
939
940 return 0;
941 }
942
fsl_spdif_bypass_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)943 static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol,
944 struct snd_ctl_elem_value *ucontrol)
945 {
946 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
947 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);
948 struct snd_soc_card *card = dai->component->card;
949 bool set = (ucontrol->value.integer.value[0] != 0);
950 struct regmap *regmap = priv->regmap;
951 struct snd_soc_pcm_runtime *rtd;
952 u32 scr, mask;
953 int stream;
954
955 rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
956
957 if (priv->bypass == set)
958 return 0; /* nothing to do */
959
960 if (snd_soc_dai_active(dai)) {
961 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n");
962 return -EBUSY;
963 }
964
965 pm_runtime_get_sync(dai->dev);
966
967 if (set) {
968 /* Disable interrupts */
969 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
970
971 /* Configure BYPASS mode */
972 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF;
973 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK |
974 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK;
975 /* Power up SPDIF module */
976 mask |= SCR_LOW_POWER;
977 } else {
978 /* Power down SPDIF module, disable TX */
979 scr = SCR_LOW_POWER | SCR_TXSEL_OFF;
980 mask = SCR_LOW_POWER | SCR_TXSEL_MASK;
981 }
982
983 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
984
985 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */
986 for_each_pcm_streams(stream)
987 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1);
988
989 priv->bypass = set;
990 pm_runtime_put_sync(dai->dev);
991
992 return 0;
993 }
994
995 /* DPLL lock information */
fsl_spdif_rxrate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)996 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
997 struct snd_ctl_elem_info *uinfo)
998 {
999 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1000 uinfo->count = 1;
1001 uinfo->value.integer.min = 16000;
1002 uinfo->value.integer.max = 192000;
1003
1004 return 0;
1005 }
1006
1007 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
1008 24, 16, 12, 8, 6, 4, 3,
1009 };
1010
1011 /* Get RX data clock rate given the SPDIF bus_clk */
spdif_get_rxclk_rate(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel)1012 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
1013 enum spdif_gainsel gainsel)
1014 {
1015 struct regmap *regmap = spdif_priv->regmap;
1016 struct platform_device *pdev = spdif_priv->pdev;
1017 u64 tmpval64, busclk_freq = 0;
1018 u32 freqmeas, phaseconf;
1019 u8 clksrc;
1020
1021 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
1022 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
1023
1024 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
1025
1026 /* Get bus clock from system */
1027 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
1028 busclk_freq = clk_get_rate(spdif_priv->sysclk);
1029
1030 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
1031 tmpval64 = (u64) busclk_freq * freqmeas;
1032 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
1033 do_div(tmpval64, 128 * 1024);
1034
1035 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
1036 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
1037 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
1038
1039 return (int)tmpval64;
1040 }
1041
1042 /*
1043 * Get DPLL lock or not info from stable interrupt status register.
1044 * User application must use this control to get locked,
1045 * then can do next PCM operation
1046 */
fsl_spdif_rxrate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1047 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
1048 struct snd_ctl_elem_value *ucontrol)
1049 {
1050 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1051 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
1052 int rate = 0;
1053
1054 if (spdif_priv->dpll_locked)
1055 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
1056
1057 ucontrol->value.integer.value[0] = rate;
1058
1059 return 0;
1060 }
1061
1062 /*
1063 * User bit sync mode:
1064 * 1 CD User channel subcode
1065 * 0 Non-CD data
1066 */
fsl_spdif_usync_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1067 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
1068 struct snd_ctl_elem_value *ucontrol)
1069 {
1070 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1071 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
1072 struct regmap *regmap = spdif_priv->regmap;
1073 u32 val;
1074
1075 regmap_read(regmap, REG_SPDIF_SRCD, &val);
1076 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
1077
1078 return 0;
1079 }
1080
1081 /*
1082 * User bit sync mode:
1083 * 1 CD User channel subcode
1084 * 0 Non-CD data
1085 */
fsl_spdif_usync_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1086 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
1087 struct snd_ctl_elem_value *ucontrol)
1088 {
1089 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
1090 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
1091 struct regmap *regmap = spdif_priv->regmap;
1092 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
1093
1094 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
1095
1096 return 0;
1097 }
1098
1099 /* FSL SPDIF IEC958 controller defines */
1100 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
1101 /* Status cchanel controller */
1102 {
1103 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1104 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1105 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1106 SNDRV_CTL_ELEM_ACCESS_WRITE |
1107 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1108 .info = fsl_spdif_info,
1109 .get = fsl_spdif_pb_get,
1110 .put = fsl_spdif_pb_put,
1111 },
1112 {
1113 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1114 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
1115 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1116 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1117 .info = fsl_spdif_info,
1118 .get = fsl_spdif_capture_get,
1119 },
1120 /* User bits controller */
1121 {
1122 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1123 .name = "IEC958 Subcode Capture Default",
1124 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1125 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1126 .info = fsl_spdif_info,
1127 .get = fsl_spdif_subcode_get,
1128 },
1129 {
1130 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1131 .name = "IEC958 Q-subcode Capture Default",
1132 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1133 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1134 .info = fsl_spdif_qinfo,
1135 .get = fsl_spdif_qget,
1136 },
1137 /* Valid bit error controller */
1138 {
1139 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1140 .name = "IEC958 RX V-Bit Errors",
1141 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1142 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1143 .info = snd_ctl_boolean_mono_info,
1144 .get = fsl_spdif_rx_vbit_get,
1145 },
1146 {
1147 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1148 .name = "IEC958 TX V-Bit",
1149 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1150 SNDRV_CTL_ELEM_ACCESS_WRITE |
1151 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1152 .info = snd_ctl_boolean_mono_info,
1153 .get = fsl_spdif_tx_vbit_get,
1154 .put = fsl_spdif_tx_vbit_put,
1155 },
1156 /* DPLL lock info get controller */
1157 {
1158 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1159 .name = "RX Sample Rate",
1160 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1161 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1162 .info = fsl_spdif_rxrate_info,
1163 .get = fsl_spdif_rxrate_get,
1164 },
1165 /* RX bypass controller */
1166 {
1167 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1168 .name = "Bypass Mode",
1169 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
1170 .info = snd_ctl_boolean_mono_info,
1171 .get = fsl_spdif_bypass_get,
1172 .put = fsl_spdif_bypass_put,
1173 },
1174 /* User bit sync mode set/get controller */
1175 {
1176 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1177 .name = "IEC958 USyncMode CDText",
1178 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1179 SNDRV_CTL_ELEM_ACCESS_WRITE |
1180 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1181 .info = snd_ctl_boolean_mono_info,
1182 .get = fsl_spdif_usync_get,
1183 .put = fsl_spdif_usync_put,
1184 },
1185 };
1186
1187 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = {
1188 {
1189 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1190 .name = "IEC958 Raw Capture Mode",
1191 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1192 SNDRV_CTL_ELEM_ACCESS_WRITE |
1193 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1194 .info = snd_ctl_boolean_mono_info,
1195 .get = fsl_spdif_rx_rcm_get,
1196 .put = fsl_spdif_rx_rcm_put,
1197 },
1198 };
1199
fsl_spdif_dai_probe(struct snd_soc_dai * dai)1200 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
1201 {
1202 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
1203
1204 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
1205 &spdif_private->dma_params_rx);
1206
1207 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
1208
1209 if (spdif_private->soc->raw_capture_mode)
1210 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm,
1211 ARRAY_SIZE(fsl_spdif_ctrls_rcm));
1212
1213 /*Clear the val bit for Tx*/
1214 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
1215 SCR_VAL_MASK, SCR_VAL_CLEAR);
1216
1217 return 0;
1218 }
1219
1220 static struct snd_soc_dai_driver fsl_spdif_dai = {
1221 .probe = &fsl_spdif_dai_probe,
1222 .playback = {
1223 .stream_name = "CPU-Playback",
1224 .channels_min = 2,
1225 .channels_max = 2,
1226 .rates = FSL_SPDIF_RATES_PLAYBACK,
1227 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1228 },
1229 .capture = {
1230 .stream_name = "CPU-Capture",
1231 .channels_min = 2,
1232 .channels_max = 2,
1233 .rates = FSL_SPDIF_RATES_CAPTURE,
1234 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1235 },
1236 .ops = &fsl_spdif_dai_ops,
1237 };
1238
1239 static const struct snd_soc_component_driver fsl_spdif_component = {
1240 .name = "fsl-spdif",
1241 };
1242
1243 /* FSL SPDIF REGMAP */
1244 static const struct reg_default fsl_spdif_reg_defaults[] = {
1245 {REG_SPDIF_SCR, 0x00000400},
1246 {REG_SPDIF_SRCD, 0x00000000},
1247 {REG_SPDIF_SIE, 0x00000000},
1248 {REG_SPDIF_STL, 0x00000000},
1249 {REG_SPDIF_STR, 0x00000000},
1250 {REG_SPDIF_STCSCH, 0x00000000},
1251 {REG_SPDIF_STCSCL, 0x00000000},
1252 {REG_SPDIF_STCSPH, 0x00000000},
1253 {REG_SPDIF_STCSPL, 0x00000000},
1254 {REG_SPDIF_STC, 0x00020f00},
1255 };
1256
fsl_spdif_readable_reg(struct device * dev,unsigned int reg)1257 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1258 {
1259 switch (reg) {
1260 case REG_SPDIF_SCR:
1261 case REG_SPDIF_SRCD:
1262 case REG_SPDIF_SRPC:
1263 case REG_SPDIF_SIE:
1264 case REG_SPDIF_SIS:
1265 case REG_SPDIF_SRL:
1266 case REG_SPDIF_SRR:
1267 case REG_SPDIF_SRCSH:
1268 case REG_SPDIF_SRCSL:
1269 case REG_SPDIF_SRU:
1270 case REG_SPDIF_SRQ:
1271 case REG_SPDIF_STCSCH:
1272 case REG_SPDIF_STCSCL:
1273 case REG_SPDIF_STCSPH:
1274 case REG_SPDIF_STCSPL:
1275 case REG_SPDIF_SRFM:
1276 case REG_SPDIF_STC:
1277 case REG_SPDIF_SRCCA_31_0:
1278 case REG_SPDIF_SRCCA_63_32:
1279 case REG_SPDIF_SRCCA_95_64:
1280 case REG_SPDIF_SRCCA_127_96:
1281 case REG_SPDIF_SRCCA_159_128:
1282 case REG_SPDIF_SRCCA_191_160:
1283 case REG_SPDIF_STCCA_31_0:
1284 case REG_SPDIF_STCCA_63_32:
1285 case REG_SPDIF_STCCA_95_64:
1286 case REG_SPDIF_STCCA_127_96:
1287 case REG_SPDIF_STCCA_159_128:
1288 case REG_SPDIF_STCCA_191_160:
1289 return true;
1290 default:
1291 return false;
1292 }
1293 }
1294
fsl_spdif_volatile_reg(struct device * dev,unsigned int reg)1295 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1296 {
1297 switch (reg) {
1298 case REG_SPDIF_SRPC:
1299 case REG_SPDIF_SIS:
1300 case REG_SPDIF_SRL:
1301 case REG_SPDIF_SRR:
1302 case REG_SPDIF_SRCSH:
1303 case REG_SPDIF_SRCSL:
1304 case REG_SPDIF_SRU:
1305 case REG_SPDIF_SRQ:
1306 case REG_SPDIF_SRFM:
1307 case REG_SPDIF_SRCCA_31_0:
1308 case REG_SPDIF_SRCCA_63_32:
1309 case REG_SPDIF_SRCCA_95_64:
1310 case REG_SPDIF_SRCCA_127_96:
1311 case REG_SPDIF_SRCCA_159_128:
1312 case REG_SPDIF_SRCCA_191_160:
1313 return true;
1314 default:
1315 return false;
1316 }
1317 }
1318
fsl_spdif_writeable_reg(struct device * dev,unsigned int reg)1319 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1320 {
1321 switch (reg) {
1322 case REG_SPDIF_SCR:
1323 case REG_SPDIF_SRCD:
1324 case REG_SPDIF_SRPC:
1325 case REG_SPDIF_SIE:
1326 case REG_SPDIF_SIC:
1327 case REG_SPDIF_STL:
1328 case REG_SPDIF_STR:
1329 case REG_SPDIF_STCSCH:
1330 case REG_SPDIF_STCSCL:
1331 case REG_SPDIF_STCSPH:
1332 case REG_SPDIF_STCSPL:
1333 case REG_SPDIF_STC:
1334 case REG_SPDIF_STCCA_31_0:
1335 case REG_SPDIF_STCCA_63_32:
1336 case REG_SPDIF_STCCA_95_64:
1337 case REG_SPDIF_STCCA_127_96:
1338 case REG_SPDIF_STCCA_159_128:
1339 case REG_SPDIF_STCCA_191_160:
1340 return true;
1341 default:
1342 return false;
1343 }
1344 }
1345
1346 static const struct regmap_config fsl_spdif_regmap_config = {
1347 .reg_bits = 32,
1348 .reg_stride = 4,
1349 .val_bits = 32,
1350
1351 .max_register = REG_SPDIF_STCCA_191_160,
1352 .reg_defaults = fsl_spdif_reg_defaults,
1353 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1354 .readable_reg = fsl_spdif_readable_reg,
1355 .volatile_reg = fsl_spdif_volatile_reg,
1356 .writeable_reg = fsl_spdif_writeable_reg,
1357 .cache_type = REGCACHE_FLAT,
1358 };
1359
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv * spdif_priv,struct clk * clk,u64 savesub,enum spdif_txrate index,bool round)1360 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1361 struct clk *clk, u64 savesub,
1362 enum spdif_txrate index, bool round)
1363 {
1364 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1365 192000, };
1366 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1367 u64 rate_ideal, rate_actual, sub;
1368 u32 arate;
1369 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1370 u8 txclk_df;
1371
1372 /* The sysclk has an extra divisor [2, 512] */
1373 sysclk_dfmin = is_sysclk ? 2 : 1;
1374 sysclk_dfmax = is_sysclk ? 512 : 1;
1375
1376 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1377 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1378 rate_ideal = rate[index] * txclk_df * 64ULL;
1379 if (round)
1380 rate_actual = clk_round_rate(clk, rate_ideal);
1381 else
1382 rate_actual = clk_get_rate(clk);
1383
1384 arate = rate_actual / 64;
1385 arate /= txclk_df * sysclk_df;
1386
1387 if (arate == rate[index]) {
1388 /* We are lucky */
1389 savesub = 0;
1390 spdif_priv->txclk_df[index] = txclk_df;
1391 spdif_priv->sysclk_df[index] = sysclk_df;
1392 spdif_priv->txrate[index] = arate;
1393 goto out;
1394 } else if (arate / rate[index] == 1) {
1395 /* A little bigger than expect */
1396 sub = (u64)(arate - rate[index]) * 100000;
1397 do_div(sub, rate[index]);
1398 if (sub >= savesub)
1399 continue;
1400 savesub = sub;
1401 spdif_priv->txclk_df[index] = txclk_df;
1402 spdif_priv->sysclk_df[index] = sysclk_df;
1403 spdif_priv->txrate[index] = arate;
1404 } else if (rate[index] / arate == 1) {
1405 /* A little smaller than expect */
1406 sub = (u64)(rate[index] - arate) * 100000;
1407 do_div(sub, rate[index]);
1408 if (sub >= savesub)
1409 continue;
1410 savesub = sub;
1411 spdif_priv->txclk_df[index] = txclk_df;
1412 spdif_priv->sysclk_df[index] = sysclk_df;
1413 spdif_priv->txrate[index] = arate;
1414 }
1415 }
1416 }
1417
1418 out:
1419 return savesub;
1420 }
1421
fsl_spdif_probe_txclk(struct fsl_spdif_priv * spdif_priv,enum spdif_txrate index)1422 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1423 enum spdif_txrate index)
1424 {
1425 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1426 192000, };
1427 struct platform_device *pdev = spdif_priv->pdev;
1428 struct device *dev = &pdev->dev;
1429 u64 savesub = 100000, ret;
1430 struct clk *clk;
1431 int i;
1432
1433 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1434 clk = spdif_priv->txclk[i];
1435 if (IS_ERR(clk)) {
1436 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1437 return PTR_ERR(clk);
1438 }
1439 if (!clk_get_rate(clk))
1440 continue;
1441
1442 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1443 fsl_spdif_can_set_clk_rate(spdif_priv, i));
1444 if (savesub == ret)
1445 continue;
1446
1447 savesub = ret;
1448 spdif_priv->txclk_src[index] = i;
1449
1450 /* To quick catch a divisor, we allow a 0.1% deviation */
1451 if (savesub < 100)
1452 break;
1453 }
1454
1455 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1456 spdif_priv->txclk_src[index], rate[index]);
1457 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
1458 spdif_priv->txclk_df[index], rate[index]);
1459 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk))
1460 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
1461 spdif_priv->sysclk_df[index], rate[index]);
1462 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
1463 rate[index], spdif_priv->txrate[index]);
1464
1465 return 0;
1466 }
1467
fsl_spdif_probe(struct platform_device * pdev)1468 static int fsl_spdif_probe(struct platform_device *pdev)
1469 {
1470 struct fsl_spdif_priv *spdif_priv;
1471 struct spdif_mixer_control *ctrl;
1472 struct resource *res;
1473 void __iomem *regs;
1474 int irq, ret, i;
1475 char tmp[16];
1476
1477 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1478 if (!spdif_priv)
1479 return -ENOMEM;
1480
1481 spdif_priv->pdev = pdev;
1482
1483 spdif_priv->soc = of_device_get_match_data(&pdev->dev);
1484
1485 /* Initialize this copy of the CPU DAI driver structure */
1486 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1487 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1488 spdif_priv->cpu_dai_drv.playback.formats =
1489 spdif_priv->soc->tx_formats;
1490
1491 /* Get the addresses and IRQ */
1492 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1493 if (IS_ERR(regs))
1494 return PTR_ERR(regs);
1495
1496 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);
1497 if (IS_ERR(spdif_priv->regmap)) {
1498 dev_err(&pdev->dev, "regmap init failed\n");
1499 return PTR_ERR(spdif_priv->regmap);
1500 }
1501
1502 for (i = 0; i < spdif_priv->soc->interrupts; i++) {
1503 irq = platform_get_irq(pdev, i);
1504 if (irq < 0)
1505 return irq;
1506
1507 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1508 dev_name(&pdev->dev), spdif_priv);
1509 if (ret) {
1510 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1511 return ret;
1512 }
1513 }
1514
1515 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1516 sprintf(tmp, "rxtx%d", i);
1517 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp);
1518 if (IS_ERR(spdif_priv->txclk[i])) {
1519 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i);
1520 return PTR_ERR(spdif_priv->txclk[i]);
1521 }
1522 }
1523
1524 /* Get system clock for rx clock rate calculation */
1525 spdif_priv->sysclk = spdif_priv->txclk[5];
1526 if (IS_ERR(spdif_priv->sysclk)) {
1527 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1528 return PTR_ERR(spdif_priv->sysclk);
1529 }
1530
1531 /* Get core clock for data register access via DMA */
1532 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1533 if (IS_ERR(spdif_priv->coreclk)) {
1534 dev_err(&pdev->dev, "no core clock in devicetree\n");
1535 return PTR_ERR(spdif_priv->coreclk);
1536 }
1537
1538 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1539 if (IS_ERR(spdif_priv->spbaclk))
1540 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1541
1542 /* Select clock source for rx/tx clock */
1543 spdif_priv->rxclk = spdif_priv->txclk[1];
1544 if (IS_ERR(spdif_priv->rxclk)) {
1545 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1546 return PTR_ERR(spdif_priv->rxclk);
1547 }
1548 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1549
1550 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1551 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1552 if (ret)
1553 return ret;
1554 }
1555
1556 /* Initial spinlock for control data */
1557 ctrl = &spdif_priv->fsl_spdif_control;
1558 spin_lock_init(&ctrl->ctl_lock);
1559
1560 /* Init tx channel status default value */
1561 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1562 IEC958_AES0_CON_EMPHASIS_5015;
1563 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1564 ctrl->ch_status[2] = 0x00;
1565 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1566 IEC958_AES3_CON_CLOCK_1000PPM;
1567
1568 spdif_priv->dpll_locked = false;
1569
1570 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;
1571 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;
1572 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1573 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1574
1575 /* Register with ASoC */
1576 dev_set_drvdata(&pdev->dev, spdif_priv);
1577 pm_runtime_enable(&pdev->dev);
1578 regcache_cache_only(spdif_priv->regmap, true);
1579
1580 /*
1581 * Register platform component before registering cpu dai for there
1582 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1583 */
1584 ret = imx_pcm_dma_init(pdev);
1585 if (ret) {
1586 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
1587 goto err_pm_disable;
1588 }
1589
1590 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1591 &spdif_priv->cpu_dai_drv, 1);
1592 if (ret) {
1593 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1594 goto err_pm_disable;
1595 }
1596
1597 return ret;
1598
1599 err_pm_disable:
1600 pm_runtime_disable(&pdev->dev);
1601 return ret;
1602 }
1603
fsl_spdif_remove(struct platform_device * pdev)1604 static int fsl_spdif_remove(struct platform_device *pdev)
1605 {
1606 pm_runtime_disable(&pdev->dev);
1607
1608 return 0;
1609 }
1610
1611 #ifdef CONFIG_PM
fsl_spdif_runtime_suspend(struct device * dev)1612 static int fsl_spdif_runtime_suspend(struct device *dev)
1613 {
1614 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1615 int i;
1616
1617 /* Disable all the interrupts */
1618 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
1619
1620 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1621 &spdif_priv->regcache_srpc);
1622 regcache_cache_only(spdif_priv->regmap, true);
1623
1624 for (i = 0; i < STC_TXCLK_SRC_MAX; i++)
1625 clk_disable_unprepare(spdif_priv->txclk[i]);
1626
1627 if (!IS_ERR(spdif_priv->spbaclk))
1628 clk_disable_unprepare(spdif_priv->spbaclk);
1629 clk_disable_unprepare(spdif_priv->coreclk);
1630
1631 return 0;
1632 }
1633
fsl_spdif_runtime_resume(struct device * dev)1634 static int fsl_spdif_runtime_resume(struct device *dev)
1635 {
1636 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1637 int ret;
1638 int i;
1639
1640 ret = clk_prepare_enable(spdif_priv->coreclk);
1641 if (ret) {
1642 dev_err(dev, "failed to enable core clock\n");
1643 return ret;
1644 }
1645
1646 if (!IS_ERR(spdif_priv->spbaclk)) {
1647 ret = clk_prepare_enable(spdif_priv->spbaclk);
1648 if (ret) {
1649 dev_err(dev, "failed to enable spba clock\n");
1650 goto disable_core_clk;
1651 }
1652 }
1653
1654 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1655 ret = clk_prepare_enable(spdif_priv->txclk[i]);
1656 if (ret)
1657 goto disable_tx_clk;
1658 }
1659
1660 regcache_cache_only(spdif_priv->regmap, false);
1661 regcache_mark_dirty(spdif_priv->regmap);
1662
1663 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1664 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1665 spdif_priv->regcache_srpc);
1666
1667 ret = regcache_sync(spdif_priv->regmap);
1668 if (ret)
1669 goto disable_tx_clk;
1670
1671 return 0;
1672
1673 disable_tx_clk:
1674 for (i--; i >= 0; i--)
1675 clk_disable_unprepare(spdif_priv->txclk[i]);
1676 if (!IS_ERR(spdif_priv->spbaclk))
1677 clk_disable_unprepare(spdif_priv->spbaclk);
1678 disable_core_clk:
1679 clk_disable_unprepare(spdif_priv->coreclk);
1680
1681 return ret;
1682 }
1683 #endif /* CONFIG_PM */
1684
1685 static const struct dev_pm_ops fsl_spdif_pm = {
1686 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1687 pm_runtime_force_resume)
1688 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
1689 NULL)
1690 };
1691
1692 static const struct of_device_id fsl_spdif_dt_ids[] = {
1693 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1694 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1695 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1696 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1697 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
1698 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
1699 {}
1700 };
1701 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1702
1703 static struct platform_driver fsl_spdif_driver = {
1704 .driver = {
1705 .name = "fsl-spdif-dai",
1706 .of_match_table = fsl_spdif_dt_ids,
1707 .pm = &fsl_spdif_pm,
1708 },
1709 .probe = fsl_spdif_probe,
1710 .remove = fsl_spdif_remove,
1711 };
1712
1713 module_platform_driver(fsl_spdif_driver);
1714
1715 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1716 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1717 MODULE_LICENSE("GPL v2");
1718 MODULE_ALIAS("platform:fsl-spdif-dai");
1719