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Searched refs:SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_sh_mask.h338 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … macro
Dgc_9_0_sh_mask.h3251 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … macro
Dgc_9_1_sh_mask.h3099 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … macro
Dgc_9_4_2_sh_mask.h26764 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … macro
Dgc_10_1_0_sh_mask.h8200 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … macro
Dgc_10_3_0_sh_mask.h8532 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK … macro