1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_dp_types.h" 36 #include "dc_hw_types.h" 37 #include "dal_types.h" 38 #include "grph_object_defs.h" 39 40 #ifdef CONFIG_DRM_AMD_DC_HDCP 41 #include "dm_cp_psp.h" 42 #endif 43 44 /* forward declarations */ 45 struct dc_plane_state; 46 struct dc_stream_state; 47 struct dc_link; 48 struct dc_sink; 49 struct dal; 50 struct dc_dmub_srv; 51 52 /******************************** 53 * Environment definitions 54 ********************************/ 55 enum dce_environment { 56 DCE_ENV_PRODUCTION_DRV = 0, 57 /* Emulation on FPGA, in "Maximus" System. 58 * This environment enforces that *only* DC registers accessed. 59 * (access to non-DC registers will hang FPGA) */ 60 DCE_ENV_FPGA_MAXIMUS, 61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 62 * requirements of Diagnostics team. */ 63 DCE_ENV_DIAG, 64 /* 65 * Guest VM system, DC HW may exist but is not virtualized and 66 * should not be used. SW support for VDI only. 67 */ 68 DCE_ENV_VIRTUAL_HW 69 }; 70 71 /* Note: use these macro definitions instead of direct comparison! */ 72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 73 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 74 75 #define IS_DIAG_DC(dce_environment) \ 76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 77 78 struct dc_perf_trace { 79 unsigned long read_count; 80 unsigned long write_count; 81 unsigned long last_entry_read; 82 unsigned long last_entry_write; 83 }; 84 85 #define DC_MAX_EDID_BUFFER_SIZE 2048 86 #define DC_EDID_BLOCK_SIZE 128 87 #define MAX_SURFACE_NUM 4 88 #define NUM_PIXEL_FORMATS 10 89 #define MAX_REPEATER_CNT 8 90 91 #include "dc_ddc_types.h" 92 93 enum tiling_mode { 94 TILING_MODE_INVALID, 95 TILING_MODE_LINEAR, 96 TILING_MODE_TILED, 97 TILING_MODE_COUNT 98 }; 99 100 enum view_3d_format { 101 VIEW_3D_FORMAT_NONE = 0, 102 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 103 VIEW_3D_FORMAT_SIDE_BY_SIDE, 104 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 105 VIEW_3D_FORMAT_COUNT, 106 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 107 }; 108 109 enum plane_stereo_format { 110 PLANE_STEREO_FORMAT_NONE = 0, 111 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 112 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 113 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 114 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 115 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 116 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 117 }; 118 119 /* TODO: Find way to calculate number of bits 120 * Please increase if pixel_format enum increases 121 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 122 */ 123 124 enum dc_edid_connector_type { 125 DC_EDID_CONNECTOR_UNKNOWN = 0, 126 DC_EDID_CONNECTOR_ANALOG = 1, 127 DC_EDID_CONNECTOR_DIGITAL = 10, 128 DC_EDID_CONNECTOR_DVI = 11, 129 DC_EDID_CONNECTOR_HDMIA = 12, 130 DC_EDID_CONNECTOR_MDDI = 14, 131 DC_EDID_CONNECTOR_DISPLAYPORT = 15 132 }; 133 134 enum dc_edid_status { 135 EDID_OK, 136 EDID_BAD_INPUT, 137 EDID_NO_RESPONSE, 138 EDID_BAD_CHECKSUM, 139 EDID_THE_SAME, 140 EDID_FALL_BACK, 141 EDID_PARTIAL_VALID, 142 }; 143 144 enum act_return_status { 145 ACT_SUCCESS, 146 ACT_LINK_LOST, 147 ACT_FAILED 148 }; 149 150 /* audio capability from EDID*/ 151 struct dc_cea_audio_mode { 152 uint8_t format_code; /* ucData[0] [6:3]*/ 153 uint8_t channel_count; /* ucData[0] [2:0]*/ 154 uint8_t sample_rate; /* ucData[1]*/ 155 union { 156 uint8_t sample_size; /* for LPCM*/ 157 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 158 uint8_t max_bit_rate; 159 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 160 }; 161 }; 162 163 struct dc_edid { 164 uint32_t length; 165 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 166 }; 167 168 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 169 * is used. In this case we assume speaker location are: front left, front 170 * right and front center. */ 171 #define DEFAULT_SPEAKER_LOCATION 5 172 173 #define DC_MAX_AUDIO_DESC_COUNT 16 174 175 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 176 177 union display_content_support { 178 unsigned int raw; 179 struct { 180 unsigned int valid_content_type :1; 181 unsigned int game_content :1; 182 unsigned int cinema_content :1; 183 unsigned int photo_content :1; 184 unsigned int graphics_content :1; 185 unsigned int reserved :27; 186 } bits; 187 }; 188 189 struct dc_panel_patch { 190 unsigned int dppowerup_delay; 191 unsigned int extra_t12_ms; 192 unsigned int extra_delay_backlight_off; 193 unsigned int extra_t7_ms; 194 unsigned int skip_scdc_overwrite; 195 unsigned int delay_ignore_msa; 196 unsigned int disable_fec; 197 unsigned int extra_t3_ms; 198 unsigned int max_dsc_target_bpp_limit; 199 unsigned int skip_avmute; 200 }; 201 202 struct dc_edid_caps { 203 /* sink identification */ 204 uint16_t manufacturer_id; 205 uint16_t product_id; 206 uint32_t serial_number; 207 uint8_t manufacture_week; 208 uint8_t manufacture_year; 209 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 210 211 /* audio caps */ 212 uint8_t speaker_flags; 213 uint32_t audio_mode_count; 214 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 215 uint32_t audio_latency; 216 uint32_t video_latency; 217 218 union display_content_support content_support; 219 220 uint8_t qs_bit; 221 uint8_t qy_bit; 222 223 uint32_t max_tmds_clk_mhz; 224 225 /*HDMI 2.0 caps*/ 226 bool lte_340mcsc_scramble; 227 228 bool edid_hdmi; 229 bool hdr_supported; 230 231 struct dc_panel_patch panel_patch; 232 }; 233 234 struct dc_mode_flags { 235 /* note: part of refresh rate flag*/ 236 uint32_t INTERLACE :1; 237 /* native display timing*/ 238 uint32_t NATIVE :1; 239 /* preferred is the recommended mode, one per display */ 240 uint32_t PREFERRED :1; 241 /* true if this mode should use reduced blanking timings 242 *_not_ related to the Reduced Blanking adjustment*/ 243 uint32_t REDUCED_BLANKING :1; 244 /* note: part of refreshrate flag*/ 245 uint32_t VIDEO_OPTIMIZED_RATE :1; 246 /* should be reported to upper layers as mode_flags*/ 247 uint32_t PACKED_PIXEL_FORMAT :1; 248 /*< preferred view*/ 249 uint32_t PREFERRED_VIEW :1; 250 /* this timing should be used only in tiled mode*/ 251 uint32_t TILED_MODE :1; 252 uint32_t DSE_MODE :1; 253 /* Refresh rate divider when Miracast sink is using a 254 different rate than the output display device 255 Must be zero for wired displays and non-zero for 256 Miracast displays*/ 257 uint32_t MIRACAST_REFRESH_DIVIDER; 258 }; 259 260 261 enum dc_timing_source { 262 TIMING_SOURCE_UNDEFINED, 263 264 /* explicitly specifed by user, most important*/ 265 TIMING_SOURCE_USER_FORCED, 266 TIMING_SOURCE_USER_OVERRIDE, 267 TIMING_SOURCE_CUSTOM, 268 TIMING_SOURCE_EXPLICIT, 269 270 /* explicitly specified by the display device, more important*/ 271 TIMING_SOURCE_EDID_CEA_SVD_3D, 272 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 273 TIMING_SOURCE_EDID_CEA_SVD_420, 274 TIMING_SOURCE_EDID_DETAILED, 275 TIMING_SOURCE_EDID_ESTABLISHED, 276 TIMING_SOURCE_EDID_STANDARD, 277 TIMING_SOURCE_EDID_CEA_SVD, 278 TIMING_SOURCE_EDID_CVT_3BYTE, 279 TIMING_SOURCE_EDID_4BYTE, 280 TIMING_SOURCE_VBIOS, 281 TIMING_SOURCE_CV, 282 TIMING_SOURCE_TV, 283 TIMING_SOURCE_HDMI_VIC, 284 285 /* implicitly specified by display device, still safe but less important*/ 286 TIMING_SOURCE_DEFAULT, 287 288 /* only used for custom base modes */ 289 TIMING_SOURCE_CUSTOM_BASE, 290 291 /* these timing might not work, least important*/ 292 TIMING_SOURCE_RANGELIMIT, 293 TIMING_SOURCE_OS_FORCED, 294 TIMING_SOURCE_IMPLICIT, 295 296 /* only used by default mode list*/ 297 TIMING_SOURCE_BASICMODE, 298 299 TIMING_SOURCE_COUNT 300 }; 301 302 303 struct stereo_3d_features { 304 bool supported ; 305 bool allTimings ; 306 bool cloneMode ; 307 bool scaling ; 308 bool singleFrameSWPacked; 309 }; 310 311 enum dc_timing_support_method { 312 TIMING_SUPPORT_METHOD_UNDEFINED, 313 TIMING_SUPPORT_METHOD_EXPLICIT, 314 TIMING_SUPPORT_METHOD_IMPLICIT, 315 TIMING_SUPPORT_METHOD_NATIVE 316 }; 317 318 struct dc_mode_info { 319 uint32_t pixel_width; 320 uint32_t pixel_height; 321 uint32_t field_rate; 322 /* Vertical refresh rate for progressive modes. 323 * Field rate for interlaced modes.*/ 324 325 enum dc_timing_standard timing_standard; 326 enum dc_timing_source timing_source; 327 struct dc_mode_flags flags; 328 }; 329 330 enum dc_power_state { 331 DC_POWER_STATE_ON = 1, 332 DC_POWER_STATE_STANDBY, 333 DC_POWER_STATE_SUSPEND, 334 DC_POWER_STATE_OFF 335 }; 336 337 /* DC PowerStates */ 338 enum dc_video_power_state { 339 DC_VIDEO_POWER_UNSPECIFIED = 0, 340 DC_VIDEO_POWER_ON = 1, 341 DC_VIDEO_POWER_STANDBY, 342 DC_VIDEO_POWER_SUSPEND, 343 DC_VIDEO_POWER_OFF, 344 DC_VIDEO_POWER_HIBERNATE, 345 DC_VIDEO_POWER_SHUTDOWN, 346 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 347 DC_VIDEO_POWER_AFTER_RESET, 348 DC_VIDEO_POWER_MAXIMUM 349 }; 350 351 enum dc_acpi_cm_power_state { 352 DC_ACPI_CM_POWER_STATE_D0 = 1, 353 DC_ACPI_CM_POWER_STATE_D1 = 2, 354 DC_ACPI_CM_POWER_STATE_D2 = 4, 355 DC_ACPI_CM_POWER_STATE_D3 = 8 356 }; 357 358 enum dc_connection_type { 359 dc_connection_none, 360 dc_connection_single, 361 dc_connection_mst_branch, 362 dc_connection_sst_branch 363 }; 364 365 struct dc_csc_adjustments { 366 struct fixed31_32 contrast; 367 struct fixed31_32 saturation; 368 struct fixed31_32 brightness; 369 struct fixed31_32 hue; 370 }; 371 372 enum dpcd_downstream_port_max_bpc { 373 DOWN_STREAM_MAX_8BPC = 0, 374 DOWN_STREAM_MAX_10BPC, 375 DOWN_STREAM_MAX_12BPC, 376 DOWN_STREAM_MAX_16BPC 377 }; 378 379 380 enum link_training_offset { 381 DPRX = 0, 382 LTTPR_PHY_REPEATER1 = 1, 383 LTTPR_PHY_REPEATER2 = 2, 384 LTTPR_PHY_REPEATER3 = 3, 385 LTTPR_PHY_REPEATER4 = 4, 386 LTTPR_PHY_REPEATER5 = 5, 387 LTTPR_PHY_REPEATER6 = 6, 388 LTTPR_PHY_REPEATER7 = 7, 389 LTTPR_PHY_REPEATER8 = 8 390 }; 391 392 struct dc_lttpr_caps { 393 union dpcd_rev revision; 394 uint8_t mode; 395 uint8_t max_lane_count; 396 uint8_t max_link_rate; 397 uint8_t phy_repeater_cnt; 398 uint8_t max_ext_timeout; 399 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 400 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 401 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 402 }; 403 404 struct dc_dongle_dfp_cap_ext { 405 bool supported; 406 uint16_t max_pixel_rate_in_mps; 407 uint16_t max_video_h_active_width; 408 uint16_t max_video_v_active_height; 409 struct dp_encoding_format_caps encoding_format_caps; 410 struct dp_color_depth_caps rgb_color_depth_caps; 411 struct dp_color_depth_caps ycbcr444_color_depth_caps; 412 struct dp_color_depth_caps ycbcr422_color_depth_caps; 413 struct dp_color_depth_caps ycbcr420_color_depth_caps; 414 }; 415 416 struct dc_dongle_caps { 417 /* dongle type (DP converter, CV smart dongle) */ 418 enum display_dongle_type dongle_type; 419 bool extendedCapValid; 420 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 421 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 422 bool is_dp_hdmi_s3d_converter; 423 bool is_dp_hdmi_ycbcr422_pass_through; 424 bool is_dp_hdmi_ycbcr420_pass_through; 425 bool is_dp_hdmi_ycbcr422_converter; 426 bool is_dp_hdmi_ycbcr420_converter; 427 uint32_t dp_hdmi_max_bpc; 428 uint32_t dp_hdmi_max_pixel_clk_in_khz; 429 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 430 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 431 }; 432 /* Scaling format */ 433 enum scaling_transformation { 434 SCALING_TRANSFORMATION_UNINITIALIZED, 435 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 436 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 437 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 438 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 439 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 440 SCALING_TRANSFORMATION_INVALID = 0x80000000, 441 442 /* Flag the first and last */ 443 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 444 SCALING_TRANSFORMATION_END = 445 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 446 }; 447 448 enum display_content_type { 449 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 450 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 451 DISPLAY_CONTENT_TYPE_PHOTO = 2, 452 DISPLAY_CONTENT_TYPE_CINEMA = 4, 453 DISPLAY_CONTENT_TYPE_GAME = 8 454 }; 455 456 enum cm_gamut_adjust_type { 457 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 458 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 459 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 460 }; 461 462 struct cm_grph_csc_adjustment { 463 struct fixed31_32 temperature_matrix[12]; 464 enum cm_gamut_adjust_type gamut_adjust_type; 465 enum cm_gamut_coef_format gamut_coef_format; 466 }; 467 468 /* writeback */ 469 struct dwb_stereo_params { 470 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 471 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 472 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 473 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 474 }; 475 476 struct dc_dwb_cnv_params { 477 unsigned int src_width; /* input active width */ 478 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 479 unsigned int crop_width; /* cropped window width at cnv output */ 480 bool crop_en; /* window cropping enable in cnv */ 481 unsigned int crop_height; /* cropped window height at cnv output */ 482 unsigned int crop_x; /* cropped window start x value at cnv output */ 483 unsigned int crop_y; /* cropped window start y value at cnv output */ 484 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 485 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 486 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 487 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 488 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 489 }; 490 491 struct dc_dwb_params { 492 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 493 unsigned int hdr_mult; /* must be in FP1.6.12 */ 494 struct cm_grph_csc_adjustment csc_params; 495 struct dwb_stereo_params stereo_params; 496 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 497 unsigned int dest_width; /* Destination width */ 498 unsigned int dest_height; /* Destination height */ 499 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 500 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 501 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 502 struct scaling_taps scaler_taps; /* Scaling taps */ 503 enum dwb_subsample_position subsample_position; 504 struct dc_transfer_func *out_transfer_func; 505 }; 506 507 /* audio*/ 508 509 union audio_sample_rates { 510 struct sample_rates { 511 uint8_t RATE_32:1; 512 uint8_t RATE_44_1:1; 513 uint8_t RATE_48:1; 514 uint8_t RATE_88_2:1; 515 uint8_t RATE_96:1; 516 uint8_t RATE_176_4:1; 517 uint8_t RATE_192:1; 518 } rate; 519 520 uint8_t all; 521 }; 522 523 struct audio_speaker_flags { 524 uint32_t FL_FR:1; 525 uint32_t LFE:1; 526 uint32_t FC:1; 527 uint32_t RL_RR:1; 528 uint32_t RC:1; 529 uint32_t FLC_FRC:1; 530 uint32_t RLC_RRC:1; 531 uint32_t SUPPORT_AI:1; 532 }; 533 534 struct audio_speaker_info { 535 uint32_t ALLSPEAKERS:7; 536 uint32_t SUPPORT_AI:1; 537 }; 538 539 540 struct audio_info_flags { 541 542 union { 543 544 struct audio_speaker_flags speaker_flags; 545 struct audio_speaker_info info; 546 547 uint8_t all; 548 }; 549 }; 550 551 enum audio_format_code { 552 AUDIO_FORMAT_CODE_FIRST = 1, 553 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 554 555 AUDIO_FORMAT_CODE_AC3, 556 /*Layers 1 & 2 */ 557 AUDIO_FORMAT_CODE_MPEG1, 558 /*MPEG1 Layer 3 */ 559 AUDIO_FORMAT_CODE_MP3, 560 /*multichannel */ 561 AUDIO_FORMAT_CODE_MPEG2, 562 AUDIO_FORMAT_CODE_AAC, 563 AUDIO_FORMAT_CODE_DTS, 564 AUDIO_FORMAT_CODE_ATRAC, 565 AUDIO_FORMAT_CODE_1BITAUDIO, 566 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 567 AUDIO_FORMAT_CODE_DTS_HD, 568 AUDIO_FORMAT_CODE_MAT_MLP, 569 AUDIO_FORMAT_CODE_DST, 570 AUDIO_FORMAT_CODE_WMAPRO, 571 AUDIO_FORMAT_CODE_LAST, 572 AUDIO_FORMAT_CODE_COUNT = 573 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 574 }; 575 576 struct audio_mode { 577 /* ucData[0] [6:3] */ 578 enum audio_format_code format_code; 579 /* ucData[0] [2:0] */ 580 uint8_t channel_count; 581 /* ucData[1] */ 582 union audio_sample_rates sample_rates; 583 union { 584 /* for LPCM */ 585 uint8_t sample_size; 586 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 587 uint8_t max_bit_rate; 588 /* for Audio Formats 9-15 */ 589 uint8_t vendor_specific; 590 }; 591 }; 592 593 struct audio_info { 594 struct audio_info_flags flags; 595 uint32_t video_latency; 596 uint32_t audio_latency; 597 uint32_t display_index; 598 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 599 uint32_t manufacture_id; 600 uint32_t product_id; 601 /* PortID used for ContainerID when defined */ 602 uint32_t port_id[2]; 603 uint32_t mode_count; 604 /* this field must be last in this struct */ 605 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 606 }; 607 struct audio_check { 608 unsigned int audio_packet_type; 609 unsigned int max_audiosample_rate; 610 unsigned int acat; 611 }; 612 enum dc_infoframe_type { 613 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 614 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 615 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 616 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 617 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 618 }; 619 620 struct dc_info_packet { 621 bool valid; 622 uint8_t hb0; 623 uint8_t hb1; 624 uint8_t hb2; 625 uint8_t hb3; 626 uint8_t sb[32]; 627 }; 628 629 struct dc_info_packet_128 { 630 bool valid; 631 uint8_t hb0; 632 uint8_t hb1; 633 uint8_t hb2; 634 uint8_t hb3; 635 uint8_t sb[128]; 636 }; 637 638 #define DC_PLANE_UPDATE_TIMES_MAX 10 639 640 struct dc_plane_flip_time { 641 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 642 unsigned int index; 643 unsigned int prev_update_time_in_us; 644 }; 645 646 enum dc_psr_state { 647 PSR_STATE0 = 0x0, 648 PSR_STATE1, 649 PSR_STATE1a, 650 PSR_STATE2, 651 PSR_STATE2a, 652 PSR_STATE2b, 653 PSR_STATE3, 654 PSR_STATE3Init, 655 PSR_STATE4, 656 PSR_STATE4a, 657 PSR_STATE4b, 658 PSR_STATE4c, 659 PSR_STATE4d, 660 PSR_STATE5, 661 PSR_STATE5a, 662 PSR_STATE5b, 663 PSR_STATE5c, 664 PSR_STATE_INVALID = 0xFF 665 }; 666 667 struct psr_config { 668 unsigned char psr_version; 669 unsigned int psr_rfb_setup_time; 670 bool psr_exit_link_training_required; 671 bool psr_frame_capture_indication_req; 672 unsigned int psr_sdp_transmit_line_num_deadline; 673 bool allow_smu_optimizations; 674 bool allow_multi_disp_optimizations; 675 }; 676 677 union dmcu_psr_level { 678 struct { 679 unsigned int SKIP_CRC:1; 680 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 681 unsigned int SKIP_PHY_POWER_DOWN:1; 682 unsigned int SKIP_AUX_ACK_CHECK:1; 683 unsigned int SKIP_CRTC_DISABLE:1; 684 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 685 unsigned int SKIP_SMU_NOTIFICATION:1; 686 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 687 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 688 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 689 unsigned int RESERVED:22; 690 } bits; 691 unsigned int u32all; 692 }; 693 694 enum physical_phy_id { 695 PHYLD_0, 696 PHYLD_1, 697 PHYLD_2, 698 PHYLD_3, 699 PHYLD_4, 700 PHYLD_5, 701 PHYLD_6, 702 PHYLD_7, 703 PHYLD_8, 704 PHYLD_9, 705 PHYLD_COUNT, 706 PHYLD_UNKNOWN = (-1L) 707 }; 708 709 enum phy_type { 710 PHY_TYPE_UNKNOWN = 1, 711 PHY_TYPE_PCIE_PHY = 2, 712 PHY_TYPE_UNIPHY = 3, 713 }; 714 715 struct psr_context { 716 /* ddc line */ 717 enum channel_id channel; 718 /* Transmitter id */ 719 enum transmitter transmitterId; 720 /* Engine Id is used for Dig Be source select */ 721 enum engine_id engineId; 722 /* Controller Id used for Dig Fe source select */ 723 enum controller_id controllerId; 724 /* Pcie or Uniphy */ 725 enum phy_type phyType; 726 /* Physical PHY Id used by SMU interpretation */ 727 enum physical_phy_id smuPhyId; 728 /* Vertical total pixels from crtc timing. 729 * This is used for static screen detection. 730 * ie. If we want to detect half a frame, 731 * we use this to determine the hyst lines. 732 */ 733 unsigned int crtcTimingVerticalTotal; 734 /* PSR supported from panel capabilities and 735 * current display configuration 736 */ 737 bool psrSupportedDisplayConfig; 738 /* Whether fast link training is supported by the panel */ 739 bool psrExitLinkTrainingRequired; 740 /* If RFB setup time is greater than the total VBLANK time, 741 * it is not possible for the sink to capture the video frame 742 * in the same frame the SDP is sent. In this case, 743 * the frame capture indication bit should be set and an extra 744 * static frame should be transmitted to the sink. 745 */ 746 bool psrFrameCaptureIndicationReq; 747 /* Set the last possible line SDP may be transmitted without violating 748 * the RFB setup time or entering the active video frame. 749 */ 750 unsigned int sdpTransmitLineNumDeadline; 751 /* The VSync rate in Hz used to calculate the 752 * step size for smooth brightness feature 753 */ 754 unsigned int vsync_rate_hz; 755 unsigned int skipPsrWaitForPllLock; 756 unsigned int numberOfControllers; 757 /* Unused, for future use. To indicate that first changed frame from 758 * state3 shouldn't result in psr_inactive, but rather to perform 759 * an automatic single frame rfb_update. 760 */ 761 bool rfb_update_auto_en; 762 /* Number of frame before entering static screen */ 763 unsigned int timehyst_frames; 764 /* Partial frames before entering static screen */ 765 unsigned int hyst_lines; 766 /* # of repeated AUX transaction attempts to make before 767 * indicating failure to the driver 768 */ 769 unsigned int aux_repeats; 770 /* Controls hw blocks to power down during PSR active state */ 771 union dmcu_psr_level psr_level; 772 /* Controls additional delay after remote frame capture before 773 * continuing powerd own 774 */ 775 unsigned int frame_delay; 776 bool allow_smu_optimizations; 777 bool allow_multi_disp_optimizations; 778 }; 779 780 struct colorspace_transform { 781 struct fixed31_32 matrix[12]; 782 bool enable_remap; 783 }; 784 785 enum i2c_mot_mode { 786 I2C_MOT_UNDEF, 787 I2C_MOT_TRUE, 788 I2C_MOT_FALSE 789 }; 790 791 struct AsicStateEx { 792 unsigned int memoryClock; 793 unsigned int displayClock; 794 unsigned int engineClock; 795 unsigned int maxSupportedDppClock; 796 unsigned int dppClock; 797 unsigned int socClock; 798 unsigned int dcfClockDeepSleep; 799 unsigned int fClock; 800 unsigned int phyClock; 801 }; 802 803 804 enum dc_clock_type { 805 DC_CLOCK_TYPE_DISPCLK = 0, 806 DC_CLOCK_TYPE_DPPCLK = 1, 807 }; 808 809 struct dc_clock_config { 810 uint32_t max_clock_khz; 811 uint32_t min_clock_khz; 812 uint32_t bw_requirequired_clock_khz; 813 uint32_t current_clock_khz;/*current clock in use*/ 814 }; 815 816 struct hw_asic_id { 817 uint32_t chip_id; 818 uint32_t chip_family; 819 uint32_t pci_revision_id; 820 uint32_t hw_internal_rev; 821 uint32_t vram_type; 822 uint32_t vram_width; 823 uint32_t feature_flags; 824 uint32_t fake_paths_num; 825 void *atombios_base_address; 826 }; 827 828 struct dc_context { 829 struct dc *dc; 830 831 void *driver_context; /* e.g. amdgpu_device */ 832 struct dc_perf_trace *perf_trace; 833 void *cgs_device; 834 835 enum dce_environment dce_environment; 836 struct hw_asic_id asic_id; 837 838 /* todo: below should probably move to dc. to facilitate removal 839 * of AS we will store these here 840 */ 841 enum dce_version dce_version; 842 struct dc_bios *dc_bios; 843 bool created_bios; 844 struct gpio_service *gpio_service; 845 uint32_t dc_sink_id_count; 846 uint32_t dc_stream_id_count; 847 uint32_t dc_edp_id_count; 848 uint64_t fbc_gpu_addr; 849 struct dc_dmub_srv *dmub_srv; 850 #ifdef CONFIG_DRM_AMD_DC_HDCP 851 struct cp_psp cp_psp; 852 #endif 853 854 }; 855 856 /* DSC DPCD capabilities */ 857 union dsc_slice_caps1 { 858 struct { 859 uint8_t NUM_SLICES_1 : 1; 860 uint8_t NUM_SLICES_2 : 1; 861 uint8_t RESERVED : 1; 862 uint8_t NUM_SLICES_4 : 1; 863 uint8_t NUM_SLICES_6 : 1; 864 uint8_t NUM_SLICES_8 : 1; 865 uint8_t NUM_SLICES_10 : 1; 866 uint8_t NUM_SLICES_12 : 1; 867 } bits; 868 uint8_t raw; 869 }; 870 871 union dsc_slice_caps2 { 872 struct { 873 uint8_t NUM_SLICES_16 : 1; 874 uint8_t NUM_SLICES_20 : 1; 875 uint8_t NUM_SLICES_24 : 1; 876 uint8_t RESERVED : 5; 877 } bits; 878 uint8_t raw; 879 }; 880 881 union dsc_color_formats { 882 struct { 883 uint8_t RGB : 1; 884 uint8_t YCBCR_444 : 1; 885 uint8_t YCBCR_SIMPLE_422 : 1; 886 uint8_t YCBCR_NATIVE_422 : 1; 887 uint8_t YCBCR_NATIVE_420 : 1; 888 uint8_t RESERVED : 3; 889 } bits; 890 uint8_t raw; 891 }; 892 893 union dsc_color_depth { 894 struct { 895 uint8_t RESERVED1 : 1; 896 uint8_t COLOR_DEPTH_8_BPC : 1; 897 uint8_t COLOR_DEPTH_10_BPC : 1; 898 uint8_t COLOR_DEPTH_12_BPC : 1; 899 uint8_t RESERVED2 : 3; 900 } bits; 901 uint8_t raw; 902 }; 903 904 struct dsc_dec_dpcd_caps { 905 bool is_dsc_supported; 906 uint8_t dsc_version; 907 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 908 union dsc_slice_caps1 slice_caps1; 909 union dsc_slice_caps2 slice_caps2; 910 int32_t lb_bit_depth; 911 bool is_block_pred_supported; 912 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 913 union dsc_color_formats color_formats; 914 union dsc_color_depth color_depth; 915 int32_t throughput_mode_0_mps; /* In MPs */ 916 int32_t throughput_mode_1_mps; /* In MPs */ 917 int32_t max_slice_width; 918 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 919 920 /* Extended DSC caps */ 921 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 922 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 923 uint32_t branch_max_line_width; 924 bool is_dp; 925 }; 926 927 struct dc_golden_table { 928 uint16_t dc_golden_table_ver; 929 uint32_t aux_dphy_rx_control0_val; 930 uint32_t aux_dphy_tx_control_val; 931 uint32_t aux_dphy_rx_control1_val; 932 uint32_t dc_gpio_aux_ctrl_0_val; 933 uint32_t dc_gpio_aux_ctrl_1_val; 934 uint32_t dc_gpio_aux_ctrl_2_val; 935 uint32_t dc_gpio_aux_ctrl_3_val; 936 uint32_t dc_gpio_aux_ctrl_4_val; 937 uint32_t dc_gpio_aux_ctrl_5_val; 938 }; 939 940 enum dc_gpu_mem_alloc_type { 941 DC_MEM_ALLOC_TYPE_GART, 942 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 943 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 944 DC_MEM_ALLOC_TYPE_AGP 945 }; 946 947 enum dc_psr_version { 948 DC_PSR_VERSION_1 = 0, 949 DC_PSR_VERSION_SU_1 = 1, 950 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 951 }; 952 953 /* Possible values of display_endpoint_id.endpoint */ 954 enum display_endpoint_type { 955 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 956 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 957 DISPLAY_ENDPOINT_UNKNOWN = -1 958 }; 959 960 /* Extends graphics_object_id with an additional member 'ep_type' for 961 * distinguishing between physical endpoints (with entries in BIOS connector table) and 962 * logical endpoints. 963 */ 964 struct display_endpoint_id { 965 struct graphics_object_id link_id; 966 enum display_endpoint_type ep_type; 967 }; 968 969 #endif /* DC_TYPES_H_ */ 970