| /linux-5.19.10/drivers/net/ethernet/sfc/siena/ |
| D | mcdi_port_common.c | 115 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ in mcdi_to_ethtool_linkset() macro
121 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
123 SET_BIT(1000baseKX_Full); in mcdi_to_ethtool_linkset()
125 SET_BIT(10000baseKX4_Full); in mcdi_to_ethtool_linkset()
127 SET_BIT(40000baseKR4_Full); in mcdi_to_ethtool_linkset()
133 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
135 SET_BIT(1000baseT_Full); in mcdi_to_ethtool_linkset()
136 SET_BIT(1000baseX_Full); in mcdi_to_ethtool_linkset()
139 SET_BIT(10000baseCR_Full); in mcdi_to_ethtool_linkset()
140 SET_BIT(10000baseLR_Full); in mcdi_to_ethtool_linkset()
[all …]
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| /linux-5.19.10/drivers/net/ethernet/sfc/ |
| D | mcdi_port_common.c | 114 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ in mcdi_to_ethtool_linkset() macro
120 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
122 SET_BIT(1000baseKX_Full); in mcdi_to_ethtool_linkset()
124 SET_BIT(10000baseKX4_Full); in mcdi_to_ethtool_linkset()
126 SET_BIT(40000baseKR4_Full); in mcdi_to_ethtool_linkset()
132 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
134 SET_BIT(1000baseT_Full); in mcdi_to_ethtool_linkset()
135 SET_BIT(1000baseX_Full); in mcdi_to_ethtool_linkset()
138 SET_BIT(10000baseCR_Full); in mcdi_to_ethtool_linkset()
139 SET_BIT(10000baseLR_Full); in mcdi_to_ethtool_linkset()
[all …]
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| /linux-5.19.10/drivers/video/fbdev/kyro/ |
| D | STG4000VTG.c | 34 tmp |= SET_BIT(8); in DisableVGA()
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); in SetupVTG()
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| D | STG4000Ramdac.c | 104 tmp &= ~SET_BIT(31); in InitialiseRamdac()
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); in DisableRamdacOutput()
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); in EnableRamdacOutput()
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| D | STG4000InitDevice.c | 296 tmp |= SET_BIT(14); in SetCoreClockPLL()
306 tmp |= SET_BIT(14); in SetCoreClockPLL()
314 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()
318 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
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| D | STG4000OverlayDevice.c | 181 tmp |= SET_BIT(31); /* Overlay format to Planer */ in CreateOverlaySurface()
293 tmp |= SET_BIT(7); in EnableOverlayPlane()
298 tmp |= SET_BIT(1); /* video stream */ in EnableOverlayPlane()
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| D | STG4000Reg.h | 31 #define SET_BIT(n) (1<<(n)) macro
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| /linux-5.19.10/drivers/net/ethernet/apm/xgene/ |
| D | xgene_enet_ring2.c | 19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
31 ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM); in xgene_enet_ring_init()
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| D | xgene_enet_main.c | 106 SET_BIT(COHERENT)); in xgene_enet_refill_pagepool()
157 SET_BIT(COHERENT)); in xgene_enet_refill_bufpool()
360 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); in xgene_enet_work_msg()
373 SET_BIT(IC) | in xgene_enet_work_msg()
374 SET_BIT(TYPE_ETH_WORK_MESSAGE); in xgene_enet_work_msg()
447 SET_BIT(COHERENT)); in xgene_enet_setup_tx_desc()
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| /linux-5.19.10/drivers/usb/storage/ |
| D | realtek_cr.c | 120 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
574 SET_BIT(value, 2); in config_autodelink_after_power_on()
579 SET_BIT(value, 7); in config_autodelink_after_power_on()
592 SET_BIT(value, 2); in config_autodelink_after_power_on()
639 SET_BIT(value, 2); in config_autodelink_before_power_down()
655 SET_BIT(value, 0); in config_autodelink_before_power_down()
657 SET_BIT(value, 2); in config_autodelink_before_power_down()
671 SET_BIT(value, 0); in config_autodelink_before_power_down()
672 SET_BIT(value, 7); in config_autodelink_before_power_down()
676 SET_BIT(value, 2); in config_autodelink_before_power_down()
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| /linux-5.19.10/drivers/scsi/sym53c8xx_2/ |
| D | sym_nvram.c | 235 #define SET_BIT 0 macro
248 case SET_BIT: in S24C16_set_bit()
272 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_start()
284 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_stop()
294 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); in S24C16_do_bit()
488 #undef SET_BIT
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| /linux-5.19.10/include/linux/mdio/ |
| D | mdio-xgene.h | 107 #define SET_BIT(field) \ macro
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| /linux-5.19.10/drivers/crypto/qat/qat_common/ |
| D | qat_hal.c | 154 #define SET_BIT(wrd, bit) ((wrd) | 1 << (bit)) macro
170 SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) : in qat_hal_set_ae_ctx_mode()
185 SET_BIT(csr, CE_NN_MODE_BITPOS) : in qat_hal_set_ae_nn_mode()
205 SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
210 SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
215 SET_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
220 SET_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
241 SET_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS) : in qat_hal_set_ae_tindex_mode()
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| /linux-5.19.10/drivers/staging/rts5208/ |
| D | rtsx_chip.h | 325 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
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| D | rtsx_scsi.c | 421 SET_BIT(chip->lun_mc, lun); in test_unit_ready()
857 SET_BIT(chip->lun_mc, lun); in read_write()
1058 SET_BIT(chip->lun_mc, lun); in read_capacity()
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| D | sd.c | 3770 SET_BIT(chip->lun_mc, lun);
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| /linux-5.19.10/drivers/i2c/busses/ |
| D | i2c-qup.c | 120 #define SET_BIT 0x1 macro
|