Home
last modified time | relevance | path

Searched refs:SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_sh_mask.h399 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro
Dsdma0_4_0_sh_mask.h400 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 macro
Dsdma0_4_2_2_sh_mask.h406 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro
Dsdma0_4_2_sh_mask.h400 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h866 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 macro
Doss_2_4_sh_mask.h936 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 macro
Doss_3_0_1_sh_mask.h950 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 macro
Doss_3_0_sh_mask.h1456 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_sh_mask.h91 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_11_0_0_sh_mask.h45 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro
Dgc_10_1_0_sh_mask.h92 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro
Dgc_10_3_0_sh_mask.h87 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT … macro