| /linux-5.19.10/include/dt-bindings/clock/ |
| D | rk3036-cru.h | 23 #define SCLK_UART0 77 macro
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| D | exynos7-clk.h | 79 #define SCLK_UART0 2 macro
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| D | s5pv210.h | 197 #define SCLK_UART0 175 macro
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| D | rk3188-cru-common.h | 20 #define SCLK_UART0 64 macro
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| D | rk3128-cru.h | 25 #define SCLK_UART0 77 macro
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| D | rk3228-cru.h | 24 #define SCLK_UART0 77 macro
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| D | rv1108-cru.h | 22 #define SCLK_UART0 72 macro
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| D | rk3288-cru.h | 32 #define SCLK_UART0 77 macro
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| D | rk3308-cru.h | 21 #define SCLK_UART0 17 macro
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| D | rk3328-cru.h | 27 #define SCLK_UART0 38 macro
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| D | rk3368-cru.h | 30 #define SCLK_UART0 77 macro
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| D | rk3399-cru.h | 38 #define SCLK_UART0 81 macro
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| D | rk3568-cru.h | 24 #define SCLK_UART0 11 macro
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| /linux-5.19.10/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3328-cru.txt | 57 clocks = <&cru SCLK_UART0>;
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| /linux-5.19.10/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 150 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3128.c | 186 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3228.c | 200 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rv1108.c | 168 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3328.c | 253 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3188.c | 260 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3368.c | 259 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| /linux-5.19.10/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 103 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| D | s5pv210.dtsi | 320 <&clocks SCLK_UART0>;
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| /linux-5.19.10/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 600 GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
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| D | clk-exynos7.c | 673 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
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