1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/delay.h>
8 #include <linux/devm-helpers.h>
9 #include <linux/err.h>
10 #include <linux/kernel.h>
11 #include <linux/interrupt.h>
12 #include <linux/bitops.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/ktime.h>
18 #include <linux/regulator/driver.h>
19 #include <linux/regmap.h>
20 #include <linux/list.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/io.h>
23 
24 /* Pin control enable input pins. */
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE		0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0		0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1		0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2		0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3		0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT	0x10
31 
32 /* Pin control high power mode input pins. */
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE		0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0			0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1			0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2			0x04
37 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3			0x08
38 #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B		0x10
39 #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT		0x20
40 
41 /*
42  * Used with enable parameters to specify that hardware default register values
43  * should be left unaltered.
44  */
45 #define SPMI_REGULATOR_USE_HW_DEFAULT			2
46 
47 /* Soft start strength of a voltage switch type regulator */
48 enum spmi_vs_soft_start_str {
49 	SPMI_VS_SOFT_START_STR_0P05_UA = 0,
50 	SPMI_VS_SOFT_START_STR_0P25_UA,
51 	SPMI_VS_SOFT_START_STR_0P55_UA,
52 	SPMI_VS_SOFT_START_STR_0P75_UA,
53 	SPMI_VS_SOFT_START_STR_HW_DEFAULT,
54 };
55 
56 /**
57  * struct spmi_regulator_init_data - spmi-regulator initialization data
58  * @pin_ctrl_enable:        Bit mask specifying which hardware pins should be
59  *				used to enable the regulator, if any
60  *			    Value should be an ORing of
61  *				SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants.  If
62  *				the bit specified by
63  *				SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
64  *				set, then pin control enable hardware registers
65  *				will not be modified.
66  * @pin_ctrl_hpm:           Bit mask specifying which hardware pins should be
67  *				used to force the regulator into high power
68  *				mode, if any
69  *			    Value should be an ORing of
70  *				SPMI_REGULATOR_PIN_CTRL_HPM_* constants.  If
71  *				the bit specified by
72  *				SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
73  *				set, then pin control mode hardware registers
74  *				will not be modified.
75  * @vs_soft_start_strength: This parameter sets the soft start strength for
76  *				voltage switch type regulators.  Its value
77  *				should be one of SPMI_VS_SOFT_START_STR_*.  If
78  *				its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
79  *				then the soft start strength will be left at its
80  *				default hardware value.
81  */
82 struct spmi_regulator_init_data {
83 	unsigned				pin_ctrl_enable;
84 	unsigned				pin_ctrl_hpm;
85 	enum spmi_vs_soft_start_str		vs_soft_start_strength;
86 };
87 
88 /* These types correspond to unique register layouts. */
89 enum spmi_regulator_logical_type {
90 	SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
91 	SPMI_REGULATOR_LOGICAL_TYPE_LDO,
92 	SPMI_REGULATOR_LOGICAL_TYPE_VS,
93 	SPMI_REGULATOR_LOGICAL_TYPE_BOOST,
94 	SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS,
95 	SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP,
96 	SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO,
97 	SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS,
98 	SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
99 	SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO,
100 	SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426,
101 	SPMI_REGULATOR_LOGICAL_TYPE_HFS430,
102 };
103 
104 enum spmi_regulator_type {
105 	SPMI_REGULATOR_TYPE_BUCK		= 0x03,
106 	SPMI_REGULATOR_TYPE_LDO			= 0x04,
107 	SPMI_REGULATOR_TYPE_VS			= 0x05,
108 	SPMI_REGULATOR_TYPE_BOOST		= 0x1b,
109 	SPMI_REGULATOR_TYPE_FTS			= 0x1c,
110 	SPMI_REGULATOR_TYPE_BOOST_BYP		= 0x1f,
111 	SPMI_REGULATOR_TYPE_ULT_LDO		= 0x21,
112 	SPMI_REGULATOR_TYPE_ULT_BUCK		= 0x22,
113 };
114 
115 enum spmi_regulator_subtype {
116 	SPMI_REGULATOR_SUBTYPE_GP_CTL		= 0x08,
117 	SPMI_REGULATOR_SUBTYPE_RF_CTL		= 0x09,
118 	SPMI_REGULATOR_SUBTYPE_N50		= 0x01,
119 	SPMI_REGULATOR_SUBTYPE_N150		= 0x02,
120 	SPMI_REGULATOR_SUBTYPE_N300		= 0x03,
121 	SPMI_REGULATOR_SUBTYPE_N600		= 0x04,
122 	SPMI_REGULATOR_SUBTYPE_N1200		= 0x05,
123 	SPMI_REGULATOR_SUBTYPE_N600_ST		= 0x06,
124 	SPMI_REGULATOR_SUBTYPE_N1200_ST		= 0x07,
125 	SPMI_REGULATOR_SUBTYPE_N900_ST		= 0x14,
126 	SPMI_REGULATOR_SUBTYPE_N300_ST		= 0x15,
127 	SPMI_REGULATOR_SUBTYPE_P50		= 0x08,
128 	SPMI_REGULATOR_SUBTYPE_P150		= 0x09,
129 	SPMI_REGULATOR_SUBTYPE_P300		= 0x0a,
130 	SPMI_REGULATOR_SUBTYPE_P600		= 0x0b,
131 	SPMI_REGULATOR_SUBTYPE_P1200		= 0x0c,
132 	SPMI_REGULATOR_SUBTYPE_LN		= 0x10,
133 	SPMI_REGULATOR_SUBTYPE_LV_P50		= 0x28,
134 	SPMI_REGULATOR_SUBTYPE_LV_P150		= 0x29,
135 	SPMI_REGULATOR_SUBTYPE_LV_P300		= 0x2a,
136 	SPMI_REGULATOR_SUBTYPE_LV_P600		= 0x2b,
137 	SPMI_REGULATOR_SUBTYPE_LV_P1200		= 0x2c,
138 	SPMI_REGULATOR_SUBTYPE_LV_P450		= 0x2d,
139 	SPMI_REGULATOR_SUBTYPE_HT_N300_ST	= 0x30,
140 	SPMI_REGULATOR_SUBTYPE_HT_N600_ST	= 0x31,
141 	SPMI_REGULATOR_SUBTYPE_HT_N1200_ST	= 0x32,
142 	SPMI_REGULATOR_SUBTYPE_HT_LVP150	= 0x3b,
143 	SPMI_REGULATOR_SUBTYPE_HT_LVP300	= 0x3c,
144 	SPMI_REGULATOR_SUBTYPE_L660_N300_ST	= 0x42,
145 	SPMI_REGULATOR_SUBTYPE_L660_N600_ST	= 0x43,
146 	SPMI_REGULATOR_SUBTYPE_L660_P50		= 0x46,
147 	SPMI_REGULATOR_SUBTYPE_L660_P150	= 0x47,
148 	SPMI_REGULATOR_SUBTYPE_L660_P600	= 0x49,
149 	SPMI_REGULATOR_SUBTYPE_L660_LVP150	= 0x4d,
150 	SPMI_REGULATOR_SUBTYPE_L660_LVP600	= 0x4f,
151 	SPMI_REGULATOR_SUBTYPE_LV100		= 0x01,
152 	SPMI_REGULATOR_SUBTYPE_LV300		= 0x02,
153 	SPMI_REGULATOR_SUBTYPE_MV300		= 0x08,
154 	SPMI_REGULATOR_SUBTYPE_MV500		= 0x09,
155 	SPMI_REGULATOR_SUBTYPE_HDMI		= 0x10,
156 	SPMI_REGULATOR_SUBTYPE_OTG		= 0x11,
157 	SPMI_REGULATOR_SUBTYPE_5V_BOOST		= 0x01,
158 	SPMI_REGULATOR_SUBTYPE_FTS_CTL		= 0x08,
159 	SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL	= 0x09,
160 	SPMI_REGULATOR_SUBTYPE_FTS426_CTL	= 0x0a,
161 	SPMI_REGULATOR_SUBTYPE_BB_2A		= 0x01,
162 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1	= 0x0d,
163 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2	= 0x0e,
164 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3	= 0x0f,
165 	SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4	= 0x10,
166 	SPMI_REGULATOR_SUBTYPE_HFS430		= 0x0a,
167 };
168 
169 enum spmi_common_regulator_registers {
170 	SPMI_COMMON_REG_DIG_MAJOR_REV		= 0x01,
171 	SPMI_COMMON_REG_TYPE			= 0x04,
172 	SPMI_COMMON_REG_SUBTYPE			= 0x05,
173 	SPMI_COMMON_REG_VOLTAGE_RANGE		= 0x40,
174 	SPMI_COMMON_REG_VOLTAGE_SET		= 0x41,
175 	SPMI_COMMON_REG_MODE			= 0x45,
176 	SPMI_COMMON_REG_ENABLE			= 0x46,
177 	SPMI_COMMON_REG_PULL_DOWN		= 0x48,
178 	SPMI_COMMON_REG_SOFT_START		= 0x4c,
179 	SPMI_COMMON_REG_STEP_CTRL		= 0x61,
180 };
181 
182 /*
183  * Second common register layout used by newer devices starting with ftsmps426
184  * Note that some of the registers from the first common layout remain
185  * unchanged and their definition is not duplicated.
186  */
187 enum spmi_ftsmps426_regulator_registers {
188 	SPMI_FTSMPS426_REG_VOLTAGE_LSB		= 0x40,
189 	SPMI_FTSMPS426_REG_VOLTAGE_MSB		= 0x41,
190 	SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB	= 0x68,
191 	SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB	= 0x69,
192 };
193 
194 enum spmi_vs_registers {
195 	SPMI_VS_REG_OCP				= 0x4a,
196 	SPMI_VS_REG_SOFT_START			= 0x4c,
197 };
198 
199 enum spmi_boost_registers {
200 	SPMI_BOOST_REG_CURRENT_LIMIT		= 0x4a,
201 };
202 
203 enum spmi_boost_byp_registers {
204 	SPMI_BOOST_BYP_REG_CURRENT_LIMIT	= 0x4b,
205 };
206 
207 enum spmi_saw3_registers {
208 	SAW3_SECURE				= 0x00,
209 	SAW3_ID					= 0x04,
210 	SAW3_SPM_STS				= 0x0C,
211 	SAW3_AVS_STS				= 0x10,
212 	SAW3_PMIC_STS				= 0x14,
213 	SAW3_RST				= 0x18,
214 	SAW3_VCTL				= 0x1C,
215 	SAW3_AVS_CTL				= 0x20,
216 	SAW3_AVS_LIMIT				= 0x24,
217 	SAW3_AVS_DLY				= 0x28,
218 	SAW3_AVS_HYSTERESIS			= 0x2C,
219 	SAW3_SPM_STS2				= 0x38,
220 	SAW3_SPM_PMIC_DATA_3			= 0x4C,
221 	SAW3_VERSION				= 0xFD0,
222 };
223 
224 /* Used for indexing into ctrl_reg.  These are offets from 0x40 */
225 enum spmi_common_control_register_index {
226 	SPMI_COMMON_IDX_VOLTAGE_RANGE		= 0,
227 	SPMI_COMMON_IDX_VOLTAGE_SET		= 1,
228 	SPMI_COMMON_IDX_MODE			= 5,
229 	SPMI_COMMON_IDX_ENABLE			= 6,
230 };
231 
232 /* Common regulator control register layout */
233 #define SPMI_COMMON_ENABLE_MASK			0x80
234 #define SPMI_COMMON_ENABLE			0x80
235 #define SPMI_COMMON_DISABLE			0x00
236 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK	0x08
237 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK	0x04
238 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK	0x02
239 #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK	0x01
240 #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK	0x0f
241 
242 /* Common regulator mode register layout */
243 #define SPMI_COMMON_MODE_HPM_MASK		0x80
244 #define SPMI_COMMON_MODE_AUTO_MASK		0x40
245 #define SPMI_COMMON_MODE_BYPASS_MASK		0x20
246 #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK	0x10
247 #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK	0x08
248 #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK	0x04
249 #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK	0x02
250 #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK	0x01
251 #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK	0x1f
252 
253 #define SPMI_FTSMPS426_MODE_BYPASS_MASK		3
254 #define SPMI_FTSMPS426_MODE_RETENTION_MASK	4
255 #define SPMI_FTSMPS426_MODE_LPM_MASK		5
256 #define SPMI_FTSMPS426_MODE_AUTO_MASK		6
257 #define SPMI_FTSMPS426_MODE_HPM_MASK		7
258 
259 #define SPMI_FTSMPS426_MODE_MASK		0x07
260 
261 /* Common regulator pull down control register layout */
262 #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK	0x80
263 
264 /* LDO regulator current limit control register layout */
265 #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK	0x80
266 
267 /* LDO regulator soft start control register layout */
268 #define SPMI_LDO_SOFT_START_ENABLE_MASK		0x80
269 
270 /* VS regulator over current protection control register layout */
271 #define SPMI_VS_OCP_OVERRIDE			0x01
272 #define SPMI_VS_OCP_NO_OVERRIDE			0x00
273 
274 /* VS regulator soft start control register layout */
275 #define SPMI_VS_SOFT_START_ENABLE_MASK		0x80
276 #define SPMI_VS_SOFT_START_SEL_MASK		0x03
277 
278 /* Boost regulator current limit control register layout */
279 #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK	0x80
280 #define SPMI_BOOST_CURRENT_LIMIT_MASK		0x07
281 
282 #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES		10
283 #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS	30
284 #define SPMI_VS_OCP_FALL_DELAY_US		90
285 #define SPMI_VS_OCP_FAULT_DELAY_US		20000
286 
287 #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK		0x18
288 #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT	3
289 #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK	0x07
290 #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT	0
291 
292 /* Clock rate in kHz of the FTSMPS regulator reference clock. */
293 #define SPMI_FTSMPS_CLOCK_RATE		19200
294 
295 /* Minimum voltage stepper delay for each step. */
296 #define SPMI_FTSMPS_STEP_DELAY		8
297 #define SPMI_DEFAULT_STEP_DELAY		20
298 
299 /*
300  * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to
301  * adjust the step rate in order to account for oscillator variance.
302  */
303 #define SPMI_FTSMPS_STEP_MARGIN_NUM	4
304 #define SPMI_FTSMPS_STEP_MARGIN_DEN	5
305 
306 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK	0x03
307 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT	0
308 
309 /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */
310 #define SPMI_FTSMPS426_CLOCK_RATE		4800
311 
312 #define SPMI_HFS430_CLOCK_RATE			1600
313 
314 /* Minimum voltage stepper delay for each step. */
315 #define SPMI_FTSMPS426_STEP_DELAY		2
316 
317 /*
318  * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is
319  * used to adjust the step rate in order to account for oscillator variance.
320  */
321 #define SPMI_FTSMPS426_STEP_MARGIN_NUM	10
322 #define SPMI_FTSMPS426_STEP_MARGIN_DEN	11
323 
324 
325 /* VSET value to decide the range of ULT SMPS */
326 #define ULT_SMPS_RANGE_SPLIT 0x60
327 
328 /**
329  * struct spmi_voltage_range - regulator set point voltage mapping description
330  * @min_uV:		Minimum programmable output voltage resulting from
331  *			set point register value 0x00
332  * @max_uV:		Maximum programmable output voltage
333  * @step_uV:		Output voltage increase resulting from the set point
334  *			register value increasing by 1
335  * @set_point_min_uV:	Minimum allowed voltage
336  * @set_point_max_uV:	Maximum allowed voltage.  This may be tweaked in order
337  *			to pick which range should be used in the case of
338  *			overlapping set points.
339  * @n_voltages:		Number of preferred voltage set points present in this
340  *			range
341  * @range_sel:		Voltage range register value corresponding to this range
342  *
343  * The following relationships must be true for the values used in this struct:
344  * (max_uV - min_uV) % step_uV == 0
345  * (set_point_min_uV - min_uV) % step_uV == 0*
346  * (set_point_max_uV - min_uV) % step_uV == 0*
347  * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1
348  *
349  * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
350  * specify that the voltage range has meaning, but is not preferred.
351  */
352 struct spmi_voltage_range {
353 	int					min_uV;
354 	int					max_uV;
355 	int					step_uV;
356 	int					set_point_min_uV;
357 	int					set_point_max_uV;
358 	unsigned				n_voltages;
359 	u8					range_sel;
360 };
361 
362 /*
363  * The ranges specified in the spmi_voltage_set_points struct must be listed
364  * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV.
365  */
366 struct spmi_voltage_set_points {
367 	struct spmi_voltage_range		*range;
368 	int					count;
369 	unsigned				n_voltages;
370 };
371 
372 struct spmi_regulator {
373 	struct regulator_desc			desc;
374 	struct device				*dev;
375 	struct delayed_work			ocp_work;
376 	struct regmap				*regmap;
377 	struct spmi_voltage_set_points		*set_points;
378 	enum spmi_regulator_logical_type	logical_type;
379 	int					ocp_irq;
380 	int					ocp_count;
381 	int					ocp_max_retries;
382 	int					ocp_retry_delay_ms;
383 	int					hpm_min_load;
384 	int					slew_rate;
385 	ktime_t					vs_enable_time;
386 	u16					base;
387 	struct list_head			node;
388 };
389 
390 struct spmi_regulator_mapping {
391 	enum spmi_regulator_type		type;
392 	enum spmi_regulator_subtype		subtype;
393 	enum spmi_regulator_logical_type	logical_type;
394 	u32					revision_min;
395 	u32					revision_max;
396 	const struct regulator_ops		*ops;
397 	struct spmi_voltage_set_points		*set_points;
398 	int					hpm_min_load;
399 };
400 
401 struct spmi_regulator_data {
402 	const char			*name;
403 	u16				base;
404 	const char			*supply;
405 	const char			*ocp;
406 	u16				force_type;
407 };
408 
409 #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \
410 		      _logical_type, _ops_val, _set_points_val, _hpm_min_load) \
411 	{ \
412 		.type		= SPMI_REGULATOR_TYPE_##_type, \
413 		.subtype	= SPMI_REGULATOR_SUBTYPE_##_subtype, \
414 		.revision_min	= _dig_major_min, \
415 		.revision_max	= _dig_major_max, \
416 		.logical_type	= SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \
417 		.ops		= &spmi_##_ops_val##_ops, \
418 		.set_points	= &_set_points_val##_set_points, \
419 		.hpm_min_load	= _hpm_min_load, \
420 	}
421 
422 #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \
423 	{ \
424 		.type		= SPMI_REGULATOR_TYPE_VS, \
425 		.subtype	= SPMI_REGULATOR_SUBTYPE_##_subtype, \
426 		.revision_min	= _dig_major_min, \
427 		.revision_max	= _dig_major_max, \
428 		.logical_type	= SPMI_REGULATOR_LOGICAL_TYPE_VS, \
429 		.ops		= &spmi_vs_ops, \
430 	}
431 
432 #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \
433 			_set_point_max_uV, _max_uV, _step_uV) \
434 	{ \
435 		.min_uV			= _min_uV, \
436 		.max_uV			= _max_uV, \
437 		.set_point_min_uV	= _set_point_min_uV, \
438 		.set_point_max_uV	= _set_point_max_uV, \
439 		.step_uV		= _step_uV, \
440 		.range_sel		= _range_sel, \
441 	}
442 
443 #define DEFINE_SPMI_SET_POINTS(name) \
444 struct spmi_voltage_set_points name##_set_points = { \
445 	.range	= name##_ranges, \
446 	.count	= ARRAY_SIZE(name##_ranges), \
447 }
448 
449 /*
450  * These tables contain the physically available PMIC regulator voltage setpoint
451  * ranges.  Where two ranges overlap in hardware, one of the ranges is trimmed
452  * to ensure that the setpoints available to software are monotonically
453  * increasing and unique.  The set_voltage callback functions expect these
454  * properties to hold.
455  */
456 static struct spmi_voltage_range pldo_ranges[] = {
457 	SPMI_VOLTAGE_RANGE(2,  750000,  750000, 1537500, 1537500, 12500),
458 	SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000),
459 	SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000),
460 };
461 
462 static struct spmi_voltage_range nldo1_ranges[] = {
463 	SPMI_VOLTAGE_RANGE(2,  750000,  750000, 1537500, 1537500, 12500),
464 };
465 
466 static struct spmi_voltage_range nldo2_ranges[] = {
467 	SPMI_VOLTAGE_RANGE(0,  375000,       0,       0, 1537500, 12500),
468 	SPMI_VOLTAGE_RANGE(1,  375000,  375000,  768750,  768750,  6250),
469 	SPMI_VOLTAGE_RANGE(2,  750000,  775000, 1537500, 1537500, 12500),
470 };
471 
472 static struct spmi_voltage_range nldo3_ranges[] = {
473 	SPMI_VOLTAGE_RANGE(0,  375000,  375000, 1537500, 1537500, 12500),
474 	SPMI_VOLTAGE_RANGE(1,  375000,       0,       0, 1537500, 12500),
475 	SPMI_VOLTAGE_RANGE(2,  750000,       0,       0, 1537500, 12500),
476 };
477 
478 static struct spmi_voltage_range ln_ldo_ranges[] = {
479 	SPMI_VOLTAGE_RANGE(1,  690000,  690000, 1110000, 1110000, 60000),
480 	SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
481 };
482 
483 static struct spmi_voltage_range smps_ranges[] = {
484 	SPMI_VOLTAGE_RANGE(0,  375000,  375000, 1562500, 1562500, 12500),
485 	SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
486 };
487 
488 static struct spmi_voltage_range ftsmps_ranges[] = {
489 	SPMI_VOLTAGE_RANGE(0,       0,  350000, 1275000, 1275000,  5000),
490 	SPMI_VOLTAGE_RANGE(1,       0, 1280000, 2040000, 2040000, 10000),
491 };
492 
493 static struct spmi_voltage_range ftsmps2p5_ranges[] = {
494 	SPMI_VOLTAGE_RANGE(0,   80000,  350000, 1355000, 1355000,  5000),
495 	SPMI_VOLTAGE_RANGE(1,  160000, 1360000, 2200000, 2200000, 10000),
496 };
497 
498 static struct spmi_voltage_range ftsmps426_ranges[] = {
499 	SPMI_VOLTAGE_RANGE(0,       0,  320000, 1352000, 1352000,  4000),
500 };
501 
502 static struct spmi_voltage_range boost_ranges[] = {
503 	SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
504 };
505 
506 static struct spmi_voltage_range boost_byp_ranges[] = {
507 	SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
508 };
509 
510 static struct spmi_voltage_range ult_lo_smps_ranges[] = {
511 	SPMI_VOLTAGE_RANGE(0,  375000,  375000, 1562500, 1562500, 12500),
512 	SPMI_VOLTAGE_RANGE(1,  750000,       0,       0, 1525000, 25000),
513 };
514 
515 static struct spmi_voltage_range ult_ho_smps_ranges[] = {
516 	SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
517 };
518 
519 static struct spmi_voltage_range ult_nldo_ranges[] = {
520 	SPMI_VOLTAGE_RANGE(0,  375000,  375000, 1537500, 1537500, 12500),
521 };
522 
523 static struct spmi_voltage_range ult_pldo_ranges[] = {
524 	SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
525 };
526 
527 static struct spmi_voltage_range pldo660_ranges[] = {
528 	SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
529 };
530 
531 static struct spmi_voltage_range nldo660_ranges[] = {
532 	SPMI_VOLTAGE_RANGE(0,  320000,  320000, 1304000, 1304000, 8000),
533 };
534 
535 static struct spmi_voltage_range ht_lvpldo_ranges[] = {
536 	SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
537 };
538 
539 static struct spmi_voltage_range ht_nldo_ranges[] = {
540 	SPMI_VOLTAGE_RANGE(0,  312000,  312000, 1304000, 1304000, 8000),
541 };
542 
543 static struct spmi_voltage_range hfs430_ranges[] = {
544 	SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
545 };
546 
547 static DEFINE_SPMI_SET_POINTS(pldo);
548 static DEFINE_SPMI_SET_POINTS(nldo1);
549 static DEFINE_SPMI_SET_POINTS(nldo2);
550 static DEFINE_SPMI_SET_POINTS(nldo3);
551 static DEFINE_SPMI_SET_POINTS(ln_ldo);
552 static DEFINE_SPMI_SET_POINTS(smps);
553 static DEFINE_SPMI_SET_POINTS(ftsmps);
554 static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
555 static DEFINE_SPMI_SET_POINTS(ftsmps426);
556 static DEFINE_SPMI_SET_POINTS(boost);
557 static DEFINE_SPMI_SET_POINTS(boost_byp);
558 static DEFINE_SPMI_SET_POINTS(ult_lo_smps);
559 static DEFINE_SPMI_SET_POINTS(ult_ho_smps);
560 static DEFINE_SPMI_SET_POINTS(ult_nldo);
561 static DEFINE_SPMI_SET_POINTS(ult_pldo);
562 static DEFINE_SPMI_SET_POINTS(pldo660);
563 static DEFINE_SPMI_SET_POINTS(nldo660);
564 static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
565 static DEFINE_SPMI_SET_POINTS(ht_nldo);
566 static DEFINE_SPMI_SET_POINTS(hfs430);
567 
spmi_vreg_read(struct spmi_regulator * vreg,u16 addr,u8 * buf,int len)568 static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
569 				 int len)
570 {
571 	return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len);
572 }
573 
spmi_vreg_write(struct spmi_regulator * vreg,u16 addr,u8 * buf,int len)574 static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr,
575 				u8 *buf, int len)
576 {
577 	return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len);
578 }
579 
spmi_vreg_update_bits(struct spmi_regulator * vreg,u16 addr,u8 val,u8 mask)580 static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val,
581 		u8 mask)
582 {
583 	return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val);
584 }
585 
spmi_regulator_vs_enable(struct regulator_dev * rdev)586 static int spmi_regulator_vs_enable(struct regulator_dev *rdev)
587 {
588 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
589 
590 	if (vreg->ocp_irq) {
591 		vreg->ocp_count = 0;
592 		vreg->vs_enable_time = ktime_get();
593 	}
594 
595 	return regulator_enable_regmap(rdev);
596 }
597 
spmi_regulator_vs_ocp(struct regulator_dev * rdev,int lim_uA,int severity,bool enable)598 static int spmi_regulator_vs_ocp(struct regulator_dev *rdev, int lim_uA,
599 				 int severity, bool enable)
600 {
601 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
602 	u8 reg = SPMI_VS_OCP_OVERRIDE;
603 
604 	if (lim_uA || !enable || severity != REGULATOR_SEVERITY_PROT)
605 		return -EINVAL;
606 
607 	return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, &reg, 1);
608 }
609 
spmi_regulator_select_voltage(struct spmi_regulator * vreg,int min_uV,int max_uV)610 static int spmi_regulator_select_voltage(struct spmi_regulator *vreg,
611 					 int min_uV, int max_uV)
612 {
613 	const struct spmi_voltage_range *range;
614 	int uV = min_uV;
615 	int lim_min_uV, lim_max_uV, i, range_id, range_max_uV;
616 	int selector, voltage_sel;
617 
618 	/* Check if request voltage is outside of physically settable range. */
619 	lim_min_uV = vreg->set_points->range[0].set_point_min_uV;
620 	lim_max_uV =
621 	  vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV;
622 
623 	if (uV < lim_min_uV && max_uV >= lim_min_uV)
624 		uV = lim_min_uV;
625 
626 	if (uV < lim_min_uV || uV > lim_max_uV) {
627 		dev_err(vreg->dev,
628 			"request v=[%d, %d] is outside possible v=[%d, %d]\n",
629 			 min_uV, max_uV, lim_min_uV, lim_max_uV);
630 		return -EINVAL;
631 	}
632 
633 	/* Find the range which uV is inside of. */
634 	for (i = vreg->set_points->count - 1; i > 0; i--) {
635 		range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV;
636 		if (uV > range_max_uV && range_max_uV > 0)
637 			break;
638 	}
639 
640 	range_id = i;
641 	range = &vreg->set_points->range[range_id];
642 
643 	/*
644 	 * Force uV to be an allowed set point by applying a ceiling function to
645 	 * the uV value.
646 	 */
647 	voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
648 	uV = voltage_sel * range->step_uV + range->min_uV;
649 
650 	if (uV > max_uV) {
651 		dev_err(vreg->dev,
652 			"request v=[%d, %d] cannot be met by any set point; "
653 			"next set point: %d\n",
654 			min_uV, max_uV, uV);
655 		return -EINVAL;
656 	}
657 
658 	selector = 0;
659 	for (i = 0; i < range_id; i++)
660 		selector += vreg->set_points->range[i].n_voltages;
661 	selector += (uV - range->set_point_min_uV) / range->step_uV;
662 
663 	return selector;
664 }
665 
spmi_sw_selector_to_hw(struct spmi_regulator * vreg,unsigned selector,u8 * range_sel,u8 * voltage_sel)666 static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
667 				  unsigned selector, u8 *range_sel,
668 				  u8 *voltage_sel)
669 {
670 	const struct spmi_voltage_range *range, *end;
671 	unsigned offset;
672 
673 	range = vreg->set_points->range;
674 	end = range + vreg->set_points->count;
675 
676 	for (; range < end; range++) {
677 		if (selector < range->n_voltages) {
678 			/*
679 			 * hardware selectors between set point min and real
680 			 * min are invalid so we ignore them
681 			 */
682 			offset = range->set_point_min_uV - range->min_uV;
683 			offset /= range->step_uV;
684 			*voltage_sel = selector + offset;
685 			*range_sel = range->range_sel;
686 			return 0;
687 		}
688 
689 		selector -= range->n_voltages;
690 	}
691 
692 	return -EINVAL;
693 }
694 
spmi_hw_selector_to_sw(struct spmi_regulator * vreg,u8 hw_sel,const struct spmi_voltage_range * range)695 static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel,
696 				  const struct spmi_voltage_range *range)
697 {
698 	unsigned sw_sel = 0;
699 	unsigned offset, max_hw_sel;
700 	const struct spmi_voltage_range *r = vreg->set_points->range;
701 	const struct spmi_voltage_range *end = r + vreg->set_points->count;
702 
703 	for (; r < end; r++) {
704 		if (r == range && range->n_voltages) {
705 			/*
706 			 * hardware selectors between set point min and real
707 			 * min and between set point max and real max are
708 			 * invalid so we return an error if they're
709 			 * programmed into the hardware
710 			 */
711 			offset = range->set_point_min_uV - range->min_uV;
712 			offset /= range->step_uV;
713 			if (hw_sel < offset)
714 				return -EINVAL;
715 
716 			max_hw_sel = range->set_point_max_uV - range->min_uV;
717 			max_hw_sel /= range->step_uV;
718 			if (hw_sel > max_hw_sel)
719 				return -EINVAL;
720 
721 			return sw_sel + hw_sel - offset;
722 		}
723 		sw_sel += r->n_voltages;
724 	}
725 
726 	return -EINVAL;
727 }
728 
729 static const struct spmi_voltage_range *
spmi_regulator_find_range(struct spmi_regulator * vreg)730 spmi_regulator_find_range(struct spmi_regulator *vreg)
731 {
732 	u8 range_sel;
733 	const struct spmi_voltage_range *range, *end;
734 
735 	range = vreg->set_points->range;
736 	end = range + vreg->set_points->count;
737 
738 	spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1);
739 
740 	for (; range < end; range++)
741 		if (range->range_sel == range_sel)
742 			return range;
743 
744 	return NULL;
745 }
746 
spmi_regulator_select_voltage_same_range(struct spmi_regulator * vreg,int min_uV,int max_uV)747 static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
748 		int min_uV, int max_uV)
749 {
750 	const struct spmi_voltage_range *range;
751 	int uV = min_uV;
752 	int i, selector;
753 
754 	range = spmi_regulator_find_range(vreg);
755 	if (!range)
756 		goto different_range;
757 
758 	if (uV < range->min_uV && max_uV >= range->min_uV)
759 		uV = range->min_uV;
760 
761 	if (uV < range->min_uV || uV > range->max_uV) {
762 		/* Current range doesn't support the requested voltage. */
763 		goto different_range;
764 	}
765 
766 	/*
767 	 * Force uV to be an allowed set point by applying a ceiling function to
768 	 * the uV value.
769 	 */
770 	uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
771 	uV = uV * range->step_uV + range->min_uV;
772 
773 	if (uV > max_uV) {
774 		/*
775 		 * No set point in the current voltage range is within the
776 		 * requested min_uV to max_uV range.
777 		 */
778 		goto different_range;
779 	}
780 
781 	selector = 0;
782 	for (i = 0; i < vreg->set_points->count; i++) {
783 		if (uV >= vreg->set_points->range[i].set_point_min_uV
784 		    && uV <= vreg->set_points->range[i].set_point_max_uV) {
785 			selector +=
786 			    (uV - vreg->set_points->range[i].set_point_min_uV)
787 				/ vreg->set_points->range[i].step_uV;
788 			break;
789 		}
790 
791 		selector += vreg->set_points->range[i].n_voltages;
792 	}
793 
794 	if (selector >= vreg->set_points->n_voltages)
795 		goto different_range;
796 
797 	return selector;
798 
799 different_range:
800 	return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
801 }
802 
spmi_regulator_common_map_voltage(struct regulator_dev * rdev,int min_uV,int max_uV)803 static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev,
804 					     int min_uV, int max_uV)
805 {
806 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
807 
808 	/*
809 	 * Favor staying in the current voltage range if possible.  This avoids
810 	 * voltage spikes that occur when changing the voltage range.
811 	 */
812 	return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV);
813 }
814 
815 static int
spmi_regulator_common_set_voltage(struct regulator_dev * rdev,unsigned selector)816 spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector)
817 {
818 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
819 	int ret;
820 	u8 buf[2];
821 	u8 range_sel, voltage_sel;
822 
823 	ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
824 	if (ret)
825 		return ret;
826 
827 	buf[0] = range_sel;
828 	buf[1] = voltage_sel;
829 	return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2);
830 }
831 
832 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
833 					      unsigned selector);
834 
spmi_regulator_ftsmps426_set_voltage(struct regulator_dev * rdev,unsigned selector)835 static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev,
836 					      unsigned selector)
837 {
838 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
839 	u8 buf[2];
840 	int mV;
841 
842 	mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000;
843 
844 	buf[0] = mV & 0xff;
845 	buf[1] = mV >> 8;
846 	return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
847 }
848 
spmi_regulator_set_voltage_time_sel(struct regulator_dev * rdev,unsigned int old_selector,unsigned int new_selector)849 static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
850 		unsigned int old_selector, unsigned int new_selector)
851 {
852 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
853 	int diff_uV;
854 
855 	diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) -
856 		      spmi_regulator_common_list_voltage(rdev, old_selector));
857 
858 	return DIV_ROUND_UP(diff_uV, vreg->slew_rate);
859 }
860 
spmi_regulator_common_get_voltage(struct regulator_dev * rdev)861 static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev)
862 {
863 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
864 	const struct spmi_voltage_range *range;
865 	u8 voltage_sel;
866 
867 	spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
868 
869 	range = spmi_regulator_find_range(vreg);
870 	if (!range)
871 		return -EINVAL;
872 
873 	return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
874 }
875 
spmi_regulator_ftsmps426_get_voltage(struct regulator_dev * rdev)876 static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev)
877 {
878 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
879 	const struct spmi_voltage_range *range;
880 	u8 buf[2];
881 	int uV;
882 
883 	spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
884 
885 	uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000;
886 	range = vreg->set_points->range;
887 
888 	return (uV - range->set_point_min_uV) / range->step_uV;
889 }
890 
spmi_regulator_single_map_voltage(struct regulator_dev * rdev,int min_uV,int max_uV)891 static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev,
892 		int min_uV, int max_uV)
893 {
894 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
895 
896 	return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
897 }
898 
spmi_regulator_single_range_set_voltage(struct regulator_dev * rdev,unsigned selector)899 static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev,
900 						   unsigned selector)
901 {
902 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
903 	u8 sel = selector;
904 
905 	/*
906 	 * Certain types of regulators do not have a range select register so
907 	 * only voltage set register needs to be written.
908 	 */
909 	return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1);
910 }
911 
spmi_regulator_single_range_get_voltage(struct regulator_dev * rdev)912 static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev)
913 {
914 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
915 	u8 selector;
916 	int ret;
917 
918 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1);
919 	if (ret)
920 		return ret;
921 
922 	return selector;
923 }
924 
spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev * rdev,unsigned selector)925 static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev,
926 						  unsigned selector)
927 {
928 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
929 	int ret;
930 	u8 range_sel, voltage_sel;
931 
932 	ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
933 	if (ret)
934 		return ret;
935 
936 	/*
937 	 * Calculate VSET based on range
938 	 * In case of range 0: voltage_sel is a 7 bit value, can be written
939 	 *			witout any modification.
940 	 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to
941 	 *			[011].
942 	 */
943 	if (range_sel == 1)
944 		voltage_sel |= ULT_SMPS_RANGE_SPLIT;
945 
946 	return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET,
947 				     voltage_sel, 0xff);
948 }
949 
spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev * rdev)950 static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev)
951 {
952 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
953 	const struct spmi_voltage_range *range;
954 	u8 voltage_sel;
955 
956 	spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
957 
958 	range = spmi_regulator_find_range(vreg);
959 	if (!range)
960 		return -EINVAL;
961 
962 	if (range->range_sel == 1)
963 		voltage_sel &= ~ULT_SMPS_RANGE_SPLIT;
964 
965 	return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
966 }
967 
spmi_regulator_common_list_voltage(struct regulator_dev * rdev,unsigned selector)968 static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
969 			unsigned selector)
970 {
971 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
972 	int uV = 0;
973 	int i;
974 
975 	if (selector >= vreg->set_points->n_voltages)
976 		return 0;
977 
978 	for (i = 0; i < vreg->set_points->count; i++) {
979 		if (selector < vreg->set_points->range[i].n_voltages) {
980 			uV = selector * vreg->set_points->range[i].step_uV
981 				+ vreg->set_points->range[i].set_point_min_uV;
982 			break;
983 		}
984 
985 		selector -= vreg->set_points->range[i].n_voltages;
986 	}
987 
988 	return uV;
989 }
990 
991 static int
spmi_regulator_common_set_bypass(struct regulator_dev * rdev,bool enable)992 spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable)
993 {
994 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
995 	u8 mask = SPMI_COMMON_MODE_BYPASS_MASK;
996 	u8 val = 0;
997 
998 	if (enable)
999 		val = mask;
1000 
1001 	return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1002 }
1003 
1004 static int
spmi_regulator_common_get_bypass(struct regulator_dev * rdev,bool * enable)1005 spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable)
1006 {
1007 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1008 	u8 val;
1009 	int ret;
1010 
1011 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1);
1012 	*enable = val & SPMI_COMMON_MODE_BYPASS_MASK;
1013 
1014 	return ret;
1015 }
1016 
spmi_regulator_common_get_mode(struct regulator_dev * rdev)1017 static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev)
1018 {
1019 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1020 	u8 reg;
1021 
1022 	spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
1023 
1024 	reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
1025 
1026 	switch (reg) {
1027 	case SPMI_COMMON_MODE_HPM_MASK:
1028 		return REGULATOR_MODE_NORMAL;
1029 	case SPMI_COMMON_MODE_AUTO_MASK:
1030 		return REGULATOR_MODE_FAST;
1031 	default:
1032 		return REGULATOR_MODE_IDLE;
1033 	}
1034 }
1035 
spmi_regulator_ftsmps426_get_mode(struct regulator_dev * rdev)1036 static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev)
1037 {
1038 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1039 	u8 reg;
1040 
1041 	spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
1042 
1043 	switch (reg) {
1044 	case SPMI_FTSMPS426_MODE_HPM_MASK:
1045 		return REGULATOR_MODE_NORMAL;
1046 	case SPMI_FTSMPS426_MODE_AUTO_MASK:
1047 		return REGULATOR_MODE_FAST;
1048 	default:
1049 		return REGULATOR_MODE_IDLE;
1050 	}
1051 }
1052 
1053 static int
spmi_regulator_common_set_mode(struct regulator_dev * rdev,unsigned int mode)1054 spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode)
1055 {
1056 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1057 	u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
1058 	u8 val;
1059 
1060 	switch (mode) {
1061 	case REGULATOR_MODE_NORMAL:
1062 		val = SPMI_COMMON_MODE_HPM_MASK;
1063 		break;
1064 	case REGULATOR_MODE_FAST:
1065 		val = SPMI_COMMON_MODE_AUTO_MASK;
1066 		break;
1067 	default:
1068 		val = 0;
1069 		break;
1070 	}
1071 
1072 	return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1073 }
1074 
1075 static int
spmi_regulator_ftsmps426_set_mode(struct regulator_dev * rdev,unsigned int mode)1076 spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode)
1077 {
1078 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1079 	u8 mask = SPMI_FTSMPS426_MODE_MASK;
1080 	u8 val;
1081 
1082 	switch (mode) {
1083 	case REGULATOR_MODE_NORMAL:
1084 		val = SPMI_FTSMPS426_MODE_HPM_MASK;
1085 		break;
1086 	case REGULATOR_MODE_FAST:
1087 		val = SPMI_FTSMPS426_MODE_AUTO_MASK;
1088 		break;
1089 	case REGULATOR_MODE_IDLE:
1090 		val = SPMI_FTSMPS426_MODE_LPM_MASK;
1091 		break;
1092 	default:
1093 		return -EINVAL;
1094 	}
1095 
1096 	return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1097 }
1098 
1099 static int
spmi_regulator_common_set_load(struct regulator_dev * rdev,int load_uA)1100 spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA)
1101 {
1102 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1103 	unsigned int mode;
1104 
1105 	if (load_uA >= vreg->hpm_min_load)
1106 		mode = REGULATOR_MODE_NORMAL;
1107 	else
1108 		mode = REGULATOR_MODE_IDLE;
1109 
1110 	return spmi_regulator_common_set_mode(rdev, mode);
1111 }
1112 
spmi_regulator_common_set_pull_down(struct regulator_dev * rdev)1113 static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev)
1114 {
1115 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1116 	unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
1117 
1118 	return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN,
1119 				     mask, mask);
1120 }
1121 
spmi_regulator_common_set_soft_start(struct regulator_dev * rdev)1122 static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev)
1123 {
1124 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1125 	unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK;
1126 
1127 	return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START,
1128 				     mask, mask);
1129 }
1130 
spmi_regulator_set_ilim(struct regulator_dev * rdev,int ilim_uA)1131 static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA)
1132 {
1133 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1134 	enum spmi_regulator_logical_type type = vreg->logical_type;
1135 	unsigned int current_reg;
1136 	u8 reg;
1137 	u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK |
1138 		  SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
1139 	int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500;
1140 
1141 	if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST)
1142 		current_reg = SPMI_BOOST_REG_CURRENT_LIMIT;
1143 	else
1144 		current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT;
1145 
1146 	if (ilim_uA > max || ilim_uA <= 0)
1147 		return -EINVAL;
1148 
1149 	reg = (ilim_uA - 1) / 500;
1150 	reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
1151 
1152 	return spmi_vreg_update_bits(vreg, current_reg, reg, mask);
1153 }
1154 
spmi_regulator_vs_clear_ocp(struct spmi_regulator * vreg)1155 static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg)
1156 {
1157 	int ret;
1158 
1159 	ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
1160 		SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK);
1161 
1162 	vreg->vs_enable_time = ktime_get();
1163 
1164 	ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
1165 		SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK);
1166 
1167 	return ret;
1168 }
1169 
spmi_regulator_vs_ocp_work(struct work_struct * work)1170 static void spmi_regulator_vs_ocp_work(struct work_struct *work)
1171 {
1172 	struct delayed_work *dwork = to_delayed_work(work);
1173 	struct spmi_regulator *vreg
1174 		= container_of(dwork, struct spmi_regulator, ocp_work);
1175 
1176 	spmi_regulator_vs_clear_ocp(vreg);
1177 }
1178 
spmi_regulator_vs_ocp_isr(int irq,void * data)1179 static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data)
1180 {
1181 	struct spmi_regulator *vreg = data;
1182 	ktime_t ocp_irq_time;
1183 	s64 ocp_trigger_delay_us;
1184 
1185 	ocp_irq_time = ktime_get();
1186 	ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time,
1187 						vreg->vs_enable_time);
1188 
1189 	/*
1190 	 * Reset the OCP count if there is a large delay between switch enable
1191 	 * and when OCP triggers.  This is indicative of a hotplug event as
1192 	 * opposed to a fault.
1193 	 */
1194 	if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US)
1195 		vreg->ocp_count = 0;
1196 
1197 	/* Wait for switch output to settle back to 0 V after OCP triggered. */
1198 	udelay(SPMI_VS_OCP_FALL_DELAY_US);
1199 
1200 	vreg->ocp_count++;
1201 
1202 	if (vreg->ocp_count == 1) {
1203 		/* Immediately clear the over current condition. */
1204 		spmi_regulator_vs_clear_ocp(vreg);
1205 	} else if (vreg->ocp_count <= vreg->ocp_max_retries) {
1206 		/* Schedule the over current clear task to run later. */
1207 		schedule_delayed_work(&vreg->ocp_work,
1208 			msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1);
1209 	} else {
1210 		dev_err(vreg->dev,
1211 			"OCP triggered %d times; no further retries\n",
1212 			vreg->ocp_count);
1213 	}
1214 
1215 	return IRQ_HANDLED;
1216 }
1217 
1218 #define SAW3_VCTL_DATA_MASK	0xFF
1219 #define SAW3_VCTL_CLEAR_MASK	0x700FF
1220 #define SAW3_AVS_CTL_EN_MASK	0x1
1221 #define SAW3_AVS_CTL_TGGL_MASK	0x8000000
1222 #define SAW3_AVS_CTL_CLEAR_MASK	0x7efc00
1223 
1224 static struct regmap *saw_regmap;
1225 
spmi_saw_set_vdd(void * data)1226 static void spmi_saw_set_vdd(void *data)
1227 {
1228 	u32 vctl, data3, avs_ctl, pmic_sts;
1229 	bool avs_enabled = false;
1230 	unsigned long timeout;
1231 	u8 voltage_sel = *(u8 *)data;
1232 
1233 	regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl);
1234 	regmap_read(saw_regmap, SAW3_VCTL, &vctl);
1235 	regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3);
1236 
1237 	/* select the band */
1238 	vctl &= ~SAW3_VCTL_CLEAR_MASK;
1239 	vctl |= (u32)voltage_sel;
1240 
1241 	data3 &= ~SAW3_VCTL_CLEAR_MASK;
1242 	data3 |= (u32)voltage_sel;
1243 
1244 	/* If AVS is enabled, switch it off during the voltage change */
1245 	avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl;
1246 	if (avs_enabled) {
1247 		avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK;
1248 		regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
1249 	}
1250 
1251 	regmap_write(saw_regmap, SAW3_RST, 1);
1252 	regmap_write(saw_regmap, SAW3_VCTL, vctl);
1253 	regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3);
1254 
1255 	timeout = jiffies + usecs_to_jiffies(100);
1256 	do {
1257 		regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts);
1258 		pmic_sts &= SAW3_VCTL_DATA_MASK;
1259 		if (pmic_sts == (u32)voltage_sel)
1260 			break;
1261 
1262 		cpu_relax();
1263 
1264 	} while (time_before(jiffies, timeout));
1265 
1266 	/* After successful voltage change, switch the AVS back on */
1267 	if (avs_enabled) {
1268 		pmic_sts &= 0x3f;
1269 		avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK;
1270 		avs_ctl |= ((pmic_sts - 4) << 10);
1271 		avs_ctl |= (pmic_sts << 17);
1272 		avs_ctl |= SAW3_AVS_CTL_TGGL_MASK;
1273 		regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
1274 	}
1275 }
1276 
1277 static int
spmi_regulator_saw_set_voltage(struct regulator_dev * rdev,unsigned selector)1278 spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector)
1279 {
1280 	struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1281 	int ret;
1282 	u8 range_sel, voltage_sel;
1283 
1284 	ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
1285 	if (ret)
1286 		return ret;
1287 
1288 	if (0 != range_sel) {
1289 		dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \
1290 			range_sel, voltage_sel);
1291 		return -EINVAL;
1292 	}
1293 
1294 	/* Always do the SAW register writes on the first CPU */
1295 	return smp_call_function_single(0, spmi_saw_set_vdd, \
1296 					&voltage_sel, true);
1297 }
1298 
1299 static struct regulator_ops spmi_saw_ops = {};
1300 
1301 static const struct regulator_ops spmi_smps_ops = {
1302 	.enable			= regulator_enable_regmap,
1303 	.disable		= regulator_disable_regmap,
1304 	.is_enabled		= regulator_is_enabled_regmap,
1305 	.set_voltage_sel	= spmi_regulator_common_set_voltage,
1306 	.set_voltage_time_sel	= spmi_regulator_set_voltage_time_sel,
1307 	.get_voltage_sel	= spmi_regulator_common_get_voltage,
1308 	.map_voltage		= spmi_regulator_common_map_voltage,
1309 	.list_voltage		= spmi_regulator_common_list_voltage,
1310 	.set_mode		= spmi_regulator_common_set_mode,
1311 	.get_mode		= spmi_regulator_common_get_mode,
1312 	.set_load		= spmi_regulator_common_set_load,
1313 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1314 };
1315 
1316 static const struct regulator_ops spmi_ldo_ops = {
1317 	.enable			= regulator_enable_regmap,
1318 	.disable		= regulator_disable_regmap,
1319 	.is_enabled		= regulator_is_enabled_regmap,
1320 	.set_voltage_sel	= spmi_regulator_common_set_voltage,
1321 	.get_voltage_sel	= spmi_regulator_common_get_voltage,
1322 	.map_voltage		= spmi_regulator_common_map_voltage,
1323 	.list_voltage		= spmi_regulator_common_list_voltage,
1324 	.set_mode		= spmi_regulator_common_set_mode,
1325 	.get_mode		= spmi_regulator_common_get_mode,
1326 	.set_load		= spmi_regulator_common_set_load,
1327 	.set_bypass		= spmi_regulator_common_set_bypass,
1328 	.get_bypass		= spmi_regulator_common_get_bypass,
1329 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1330 	.set_soft_start		= spmi_regulator_common_set_soft_start,
1331 };
1332 
1333 static const struct regulator_ops spmi_ln_ldo_ops = {
1334 	.enable			= regulator_enable_regmap,
1335 	.disable		= regulator_disable_regmap,
1336 	.is_enabled		= regulator_is_enabled_regmap,
1337 	.set_voltage_sel	= spmi_regulator_common_set_voltage,
1338 	.get_voltage_sel	= spmi_regulator_common_get_voltage,
1339 	.map_voltage		= spmi_regulator_common_map_voltage,
1340 	.list_voltage		= spmi_regulator_common_list_voltage,
1341 	.set_bypass		= spmi_regulator_common_set_bypass,
1342 	.get_bypass		= spmi_regulator_common_get_bypass,
1343 };
1344 
1345 static const struct regulator_ops spmi_vs_ops = {
1346 	.enable			= spmi_regulator_vs_enable,
1347 	.disable		= regulator_disable_regmap,
1348 	.is_enabled		= regulator_is_enabled_regmap,
1349 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1350 	.set_soft_start		= spmi_regulator_common_set_soft_start,
1351 	.set_over_current_protection = spmi_regulator_vs_ocp,
1352 	.set_mode		= spmi_regulator_common_set_mode,
1353 	.get_mode		= spmi_regulator_common_get_mode,
1354 };
1355 
1356 static const struct regulator_ops spmi_boost_ops = {
1357 	.enable			= regulator_enable_regmap,
1358 	.disable		= regulator_disable_regmap,
1359 	.is_enabled		= regulator_is_enabled_regmap,
1360 	.set_voltage_sel	= spmi_regulator_single_range_set_voltage,
1361 	.get_voltage_sel	= spmi_regulator_single_range_get_voltage,
1362 	.map_voltage		= spmi_regulator_single_map_voltage,
1363 	.list_voltage		= spmi_regulator_common_list_voltage,
1364 	.set_input_current_limit = spmi_regulator_set_ilim,
1365 };
1366 
1367 static const struct regulator_ops spmi_ftsmps_ops = {
1368 	.enable			= regulator_enable_regmap,
1369 	.disable		= regulator_disable_regmap,
1370 	.is_enabled		= regulator_is_enabled_regmap,
1371 	.set_voltage_sel	= spmi_regulator_common_set_voltage,
1372 	.set_voltage_time_sel	= spmi_regulator_set_voltage_time_sel,
1373 	.get_voltage_sel	= spmi_regulator_common_get_voltage,
1374 	.map_voltage		= spmi_regulator_common_map_voltage,
1375 	.list_voltage		= spmi_regulator_common_list_voltage,
1376 	.set_mode		= spmi_regulator_common_set_mode,
1377 	.get_mode		= spmi_regulator_common_get_mode,
1378 	.set_load		= spmi_regulator_common_set_load,
1379 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1380 };
1381 
1382 static const struct regulator_ops spmi_ult_lo_smps_ops = {
1383 	.enable			= regulator_enable_regmap,
1384 	.disable		= regulator_disable_regmap,
1385 	.is_enabled		= regulator_is_enabled_regmap,
1386 	.set_voltage_sel	= spmi_regulator_ult_lo_smps_set_voltage,
1387 	.set_voltage_time_sel	= spmi_regulator_set_voltage_time_sel,
1388 	.get_voltage_sel	= spmi_regulator_ult_lo_smps_get_voltage,
1389 	.list_voltage		= spmi_regulator_common_list_voltage,
1390 	.set_mode		= spmi_regulator_common_set_mode,
1391 	.get_mode		= spmi_regulator_common_get_mode,
1392 	.set_load		= spmi_regulator_common_set_load,
1393 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1394 };
1395 
1396 static const struct regulator_ops spmi_ult_ho_smps_ops = {
1397 	.enable			= regulator_enable_regmap,
1398 	.disable		= regulator_disable_regmap,
1399 	.is_enabled		= regulator_is_enabled_regmap,
1400 	.set_voltage_sel	= spmi_regulator_single_range_set_voltage,
1401 	.set_voltage_time_sel	= spmi_regulator_set_voltage_time_sel,
1402 	.get_voltage_sel	= spmi_regulator_single_range_get_voltage,
1403 	.map_voltage		= spmi_regulator_single_map_voltage,
1404 	.list_voltage		= spmi_regulator_common_list_voltage,
1405 	.set_mode		= spmi_regulator_common_set_mode,
1406 	.get_mode		= spmi_regulator_common_get_mode,
1407 	.set_load		= spmi_regulator_common_set_load,
1408 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1409 };
1410 
1411 static const struct regulator_ops spmi_ult_ldo_ops = {
1412 	.enable			= regulator_enable_regmap,
1413 	.disable		= regulator_disable_regmap,
1414 	.is_enabled		= regulator_is_enabled_regmap,
1415 	.set_voltage_sel	= spmi_regulator_single_range_set_voltage,
1416 	.get_voltage_sel	= spmi_regulator_single_range_get_voltage,
1417 	.map_voltage		= spmi_regulator_single_map_voltage,
1418 	.list_voltage		= spmi_regulator_common_list_voltage,
1419 	.set_mode		= spmi_regulator_common_set_mode,
1420 	.get_mode		= spmi_regulator_common_get_mode,
1421 	.set_load		= spmi_regulator_common_set_load,
1422 	.set_bypass		= spmi_regulator_common_set_bypass,
1423 	.get_bypass		= spmi_regulator_common_get_bypass,
1424 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1425 	.set_soft_start		= spmi_regulator_common_set_soft_start,
1426 };
1427 
1428 static const struct regulator_ops spmi_ftsmps426_ops = {
1429 	.enable			= regulator_enable_regmap,
1430 	.disable		= regulator_disable_regmap,
1431 	.is_enabled		= regulator_is_enabled_regmap,
1432 	.set_voltage_sel	= spmi_regulator_ftsmps426_set_voltage,
1433 	.set_voltage_time_sel	= spmi_regulator_set_voltage_time_sel,
1434 	.get_voltage_sel	= spmi_regulator_ftsmps426_get_voltage,
1435 	.map_voltage		= spmi_regulator_single_map_voltage,
1436 	.list_voltage		= spmi_regulator_common_list_voltage,
1437 	.set_mode		= spmi_regulator_ftsmps426_set_mode,
1438 	.get_mode		= spmi_regulator_ftsmps426_get_mode,
1439 	.set_load		= spmi_regulator_common_set_load,
1440 	.set_pull_down		= spmi_regulator_common_set_pull_down,
1441 };
1442 
1443 static const struct regulator_ops spmi_hfs430_ops = {
1444 	.enable			= regulator_enable_regmap,
1445 	.disable		= regulator_disable_regmap,
1446 	.is_enabled		= regulator_is_enabled_regmap,
1447 	.set_voltage_sel	= spmi_regulator_ftsmps426_set_voltage,
1448 	.set_voltage_time_sel	= spmi_regulator_set_voltage_time_sel,
1449 	.get_voltage_sel	= spmi_regulator_ftsmps426_get_voltage,
1450 	.map_voltage		= spmi_regulator_single_map_voltage,
1451 	.list_voltage		= spmi_regulator_common_list_voltage,
1452 	.set_mode		= spmi_regulator_ftsmps426_set_mode,
1453 	.get_mode		= spmi_regulator_ftsmps426_get_mode,
1454 };
1455 
1456 /* Maximum possible digital major revision value */
1457 #define INF 0xFF
1458 
1459 static const struct spmi_regulator_mapping supported_regulators[] = {
1460 	/*           type subtype dig_min dig_max ltype ops setpoints hpm_min */
1461 	SPMI_VREG(BUCK,  GP_CTL,   0, INF, SMPS,   smps,   smps,   100000),
1462 	SPMI_VREG(BUCK,  HFS430,   0, INF, HFS430, hfs430, hfs430,  10000),
1463 	SPMI_VREG(LDO,   N300,     0, INF, LDO,    ldo,    nldo1,   10000),
1464 	SPMI_VREG(LDO,   N600,     0,   0, LDO,    ldo,    nldo2,   10000),
1465 	SPMI_VREG(LDO,   N1200,    0,   0, LDO,    ldo,    nldo2,   10000),
1466 	SPMI_VREG(LDO,   N600,     1, INF, LDO,    ldo,    nldo3,   10000),
1467 	SPMI_VREG(LDO,   N1200,    1, INF, LDO,    ldo,    nldo3,   10000),
1468 	SPMI_VREG(LDO,   N600_ST,  0,   0, LDO,    ldo,    nldo2,   10000),
1469 	SPMI_VREG(LDO,   N1200_ST, 0,   0, LDO,    ldo,    nldo2,   10000),
1470 	SPMI_VREG(LDO,   N600_ST,  1, INF, LDO,    ldo,    nldo3,   10000),
1471 	SPMI_VREG(LDO,   N1200_ST, 1, INF, LDO,    ldo,    nldo3,   10000),
1472 	SPMI_VREG(LDO,   P50,      0, INF, LDO,    ldo,    pldo,     5000),
1473 	SPMI_VREG(LDO,   P150,     0, INF, LDO,    ldo,    pldo,    10000),
1474 	SPMI_VREG(LDO,   P300,     0, INF, LDO,    ldo,    pldo,    10000),
1475 	SPMI_VREG(LDO,   P600,     0, INF, LDO,    ldo,    pldo,    10000),
1476 	SPMI_VREG(LDO,   P1200,    0, INF, LDO,    ldo,    pldo,    10000),
1477 	SPMI_VREG(LDO,   LN,       0, INF, LN_LDO, ln_ldo, ln_ldo,      0),
1478 	SPMI_VREG(LDO,   LV_P50,   0, INF, LDO,    ldo,    pldo,     5000),
1479 	SPMI_VREG(LDO,   LV_P150,  0, INF, LDO,    ldo,    pldo,    10000),
1480 	SPMI_VREG(LDO,   LV_P300,  0, INF, LDO,    ldo,    pldo,    10000),
1481 	SPMI_VREG(LDO,   LV_P600,  0, INF, LDO,    ldo,    pldo,    10000),
1482 	SPMI_VREG(LDO,   LV_P1200, 0, INF, LDO,    ldo,    pldo,    10000),
1483 	SPMI_VREG(LDO, HT_N300_ST,   0, INF, FTSMPS426, ftsmps426,
1484 							ht_nldo,   30000),
1485 	SPMI_VREG(LDO, HT_N600_ST,   0, INF, FTSMPS426, ftsmps426,
1486 							ht_nldo,   30000),
1487 	SPMI_VREG(LDO, HT_N1200_ST,  0, INF, FTSMPS426, ftsmps426,
1488 							ht_nldo,   30000),
1489 	SPMI_VREG(LDO, HT_LVP150,    0, INF, FTSMPS426, ftsmps426,
1490 							ht_lvpldo, 10000),
1491 	SPMI_VREG(LDO, HT_LVP300,    0, INF, FTSMPS426, ftsmps426,
1492 							ht_lvpldo, 10000),
1493 	SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1494 							nldo660,   10000),
1495 	SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1496 							nldo660,   10000),
1497 	SPMI_VREG(LDO, L660_P50,     0, INF, FTSMPS426, ftsmps426,
1498 							pldo660,   10000),
1499 	SPMI_VREG(LDO, L660_P150,    0, INF, FTSMPS426, ftsmps426,
1500 							pldo660,   10000),
1501 	SPMI_VREG(LDO, L660_P600,    0, INF, FTSMPS426, ftsmps426,
1502 							pldo660,   10000),
1503 	SPMI_VREG(LDO, L660_LVP150,  0, INF, FTSMPS426, ftsmps426,
1504 							ht_lvpldo, 10000),
1505 	SPMI_VREG(LDO, L660_LVP600,  0, INF, FTSMPS426, ftsmps426,
1506 							ht_lvpldo, 10000),
1507 	SPMI_VREG_VS(LV100,        0, INF),
1508 	SPMI_VREG_VS(LV300,        0, INF),
1509 	SPMI_VREG_VS(MV300,        0, INF),
1510 	SPMI_VREG_VS(MV500,        0, INF),
1511 	SPMI_VREG_VS(HDMI,         0, INF),
1512 	SPMI_VREG_VS(OTG,          0, INF),
1513 	SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST,  boost,  boost,       0),
1514 	SPMI_VREG(FTS,   FTS_CTL,  0, INF, FTSMPS, ftsmps, ftsmps, 100000),
1515 	SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
1516 	SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000),
1517 	SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
1518 	SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1519 						ult_lo_smps,   100000),
1520 	SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1521 						ult_lo_smps,   100000),
1522 	SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1523 						ult_lo_smps,   100000),
1524 	SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
1525 						ult_ho_smps,   100000),
1526 	SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1527 	SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1528 	SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1529 	SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1530 	SPMI_VREG(ULT_LDO, LV_P50,   0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1531 	SPMI_VREG(ULT_LDO, LV_P150,  0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1532 	SPMI_VREG(ULT_LDO, LV_P300,  0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1533 	SPMI_VREG(ULT_LDO, LV_P450,  0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1534 	SPMI_VREG(ULT_LDO, P600,     0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1535 	SPMI_VREG(ULT_LDO, P300,     0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1536 	SPMI_VREG(ULT_LDO, P150,     0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1537 	SPMI_VREG(ULT_LDO, P50,     0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
1538 };
1539 
spmi_calculate_num_voltages(struct spmi_voltage_set_points * points)1540 static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points)
1541 {
1542 	unsigned int n;
1543 	struct spmi_voltage_range *range = points->range;
1544 
1545 	for (; range < points->range + points->count; range++) {
1546 		n = 0;
1547 		if (range->set_point_max_uV) {
1548 			n = range->set_point_max_uV - range->set_point_min_uV;
1549 			n = (n / range->step_uV) + 1;
1550 		}
1551 		range->n_voltages = n;
1552 		points->n_voltages += n;
1553 	}
1554 }
1555 
spmi_regulator_match(struct spmi_regulator * vreg,u16 force_type)1556 static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type)
1557 {
1558 	const struct spmi_regulator_mapping *mapping;
1559 	int ret, i;
1560 	u32 dig_major_rev;
1561 	u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1];
1562 	u8 type, subtype;
1563 
1564 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version,
1565 		ARRAY_SIZE(version));
1566 	if (ret) {
1567 		dev_dbg(vreg->dev, "could not read version registers\n");
1568 		return ret;
1569 	}
1570 	dig_major_rev	= version[SPMI_COMMON_REG_DIG_MAJOR_REV
1571 					- SPMI_COMMON_REG_DIG_MAJOR_REV];
1572 
1573 	if (!force_type) {
1574 		type		= version[SPMI_COMMON_REG_TYPE -
1575 					  SPMI_COMMON_REG_DIG_MAJOR_REV];
1576 		subtype		= version[SPMI_COMMON_REG_SUBTYPE -
1577 					  SPMI_COMMON_REG_DIG_MAJOR_REV];
1578 	} else {
1579 		type = force_type >> 8;
1580 		subtype = force_type;
1581 	}
1582 
1583 	for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) {
1584 		mapping = &supported_regulators[i];
1585 		if (mapping->type == type && mapping->subtype == subtype
1586 		    && mapping->revision_min <= dig_major_rev
1587 		    && mapping->revision_max >= dig_major_rev)
1588 			goto found;
1589 	}
1590 
1591 	dev_err(vreg->dev,
1592 		"unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n",
1593 		vreg->desc.name, type, subtype, dig_major_rev);
1594 
1595 	return -ENODEV;
1596 
1597 found:
1598 	vreg->logical_type	= mapping->logical_type;
1599 	vreg->set_points	= mapping->set_points;
1600 	vreg->hpm_min_load	= mapping->hpm_min_load;
1601 	vreg->desc.ops		= mapping->ops;
1602 
1603 	if (mapping->set_points) {
1604 		if (!mapping->set_points->n_voltages)
1605 			spmi_calculate_num_voltages(mapping->set_points);
1606 		vreg->desc.n_voltages = mapping->set_points->n_voltages;
1607 	}
1608 
1609 	return 0;
1610 }
1611 
spmi_regulator_init_slew_rate(struct spmi_regulator * vreg)1612 static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg)
1613 {
1614 	int ret;
1615 	u8 reg = 0;
1616 	int step, delay, slew_rate, step_delay;
1617 	const struct spmi_voltage_range *range;
1618 
1619 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
1620 	if (ret) {
1621 		dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1622 		return ret;
1623 	}
1624 
1625 	range = spmi_regulator_find_range(vreg);
1626 	if (!range)
1627 		return -EINVAL;
1628 
1629 	switch (vreg->logical_type) {
1630 	case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1631 		step_delay = SPMI_FTSMPS_STEP_DELAY;
1632 		break;
1633 	default:
1634 		step_delay = SPMI_DEFAULT_STEP_DELAY;
1635 		break;
1636 	}
1637 
1638 	step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK;
1639 	step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT;
1640 
1641 	delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK;
1642 	delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT;
1643 
1644 	/* slew_rate has units of uV/us */
1645 	slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step);
1646 	slew_rate /= 1000 * (step_delay << delay);
1647 	slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM;
1648 	slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN;
1649 
1650 	/* Ensure that the slew rate is greater than 0 */
1651 	vreg->slew_rate = max(slew_rate, 1);
1652 
1653 	return ret;
1654 }
1655 
spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator * vreg,int clock_rate)1656 static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg,
1657 						   int clock_rate)
1658 {
1659 	int ret;
1660 	u8 reg = 0;
1661 	int delay, slew_rate;
1662 	const struct spmi_voltage_range *range = &vreg->set_points->range[0];
1663 
1664 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
1665 	if (ret) {
1666 		dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1667 		return ret;
1668 	}
1669 
1670 	delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK;
1671 	delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT;
1672 
1673 	/* slew_rate has units of uV/us */
1674 	slew_rate = clock_rate * range->step_uV;
1675 	slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay);
1676 	slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM;
1677 	slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN;
1678 
1679 	/* Ensure that the slew rate is greater than 0 */
1680 	vreg->slew_rate = max(slew_rate, 1);
1681 
1682 	return ret;
1683 }
1684 
spmi_regulator_init_registers(struct spmi_regulator * vreg,const struct spmi_regulator_init_data * data)1685 static int spmi_regulator_init_registers(struct spmi_regulator *vreg,
1686 				const struct spmi_regulator_init_data *data)
1687 {
1688 	int ret;
1689 	enum spmi_regulator_logical_type type;
1690 	u8 ctrl_reg[8], reg, mask;
1691 
1692 	type = vreg->logical_type;
1693 
1694 	ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1695 	if (ret)
1696 		return ret;
1697 
1698 	/* Set up enable pin control. */
1699 	if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) {
1700 		switch (type) {
1701 		case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1702 		case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
1703 		case SPMI_REGULATOR_LOGICAL_TYPE_VS:
1704 			ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
1705 				~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1706 			ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
1707 				data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1708 			break;
1709 		default:
1710 			break;
1711 		}
1712 	}
1713 
1714 	/* Set up mode pin control. */
1715 	if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
1716 		switch (type) {
1717 		case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1718 		case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
1719 			ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1720 				~SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1721 			ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1722 				data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1723 			break;
1724 		case SPMI_REGULATOR_LOGICAL_TYPE_VS:
1725 		case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1726 		case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1727 		case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO:
1728 			ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1729 				~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1730 			ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1731 				data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1732 			break;
1733 		default:
1734 			break;
1735 		}
1736 	}
1737 
1738 	/* Write back any control register values that were modified. */
1739 	ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1740 	if (ret)
1741 		return ret;
1742 
1743 	/* Set soft start strength and over current protection for VS. */
1744 	if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) {
1745 		if (data->vs_soft_start_strength
1746 				!= SPMI_VS_SOFT_START_STR_HW_DEFAULT) {
1747 			reg = data->vs_soft_start_strength
1748 				& SPMI_VS_SOFT_START_SEL_MASK;
1749 			mask = SPMI_VS_SOFT_START_SEL_MASK;
1750 			return spmi_vreg_update_bits(vreg,
1751 						     SPMI_VS_REG_SOFT_START,
1752 						     reg, mask);
1753 		}
1754 	}
1755 
1756 	return 0;
1757 }
1758 
spmi_regulator_get_dt_config(struct spmi_regulator * vreg,struct device_node * node,struct spmi_regulator_init_data * data)1759 static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg,
1760 		struct device_node *node, struct spmi_regulator_init_data *data)
1761 {
1762 	/*
1763 	 * Initialize configuration parameters to use hardware default in case
1764 	 * no value is specified via device tree.
1765 	 */
1766 	data->pin_ctrl_enable	    = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT;
1767 	data->pin_ctrl_hpm	    = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT;
1768 	data->vs_soft_start_strength	= SPMI_VS_SOFT_START_STR_HW_DEFAULT;
1769 
1770 	/* These bindings are optional, so it is okay if they aren't found. */
1771 	of_property_read_u32(node, "qcom,ocp-max-retries",
1772 		&vreg->ocp_max_retries);
1773 	of_property_read_u32(node, "qcom,ocp-retry-delay",
1774 		&vreg->ocp_retry_delay_ms);
1775 	of_property_read_u32(node, "qcom,pin-ctrl-enable",
1776 		&data->pin_ctrl_enable);
1777 	of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm);
1778 	of_property_read_u32(node, "qcom,vs-soft-start-strength",
1779 		&data->vs_soft_start_strength);
1780 }
1781 
spmi_regulator_of_map_mode(unsigned int mode)1782 static unsigned int spmi_regulator_of_map_mode(unsigned int mode)
1783 {
1784 	if (mode == 1)
1785 		return REGULATOR_MODE_NORMAL;
1786 	if (mode == 2)
1787 		return REGULATOR_MODE_FAST;
1788 
1789 	return REGULATOR_MODE_IDLE;
1790 }
1791 
spmi_regulator_of_parse(struct device_node * node,const struct regulator_desc * desc,struct regulator_config * config)1792 static int spmi_regulator_of_parse(struct device_node *node,
1793 			    const struct regulator_desc *desc,
1794 			    struct regulator_config *config)
1795 {
1796 	struct spmi_regulator_init_data data = { };
1797 	struct spmi_regulator *vreg = config->driver_data;
1798 	struct device *dev = config->dev;
1799 	int ret;
1800 
1801 	spmi_regulator_get_dt_config(vreg, node, &data);
1802 
1803 	if (!vreg->ocp_max_retries)
1804 		vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
1805 	if (!vreg->ocp_retry_delay_ms)
1806 		vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
1807 
1808 	ret = spmi_regulator_init_registers(vreg, &data);
1809 	if (ret) {
1810 		dev_err(dev, "common initialization failed, ret=%d\n", ret);
1811 		return ret;
1812 	}
1813 
1814 	switch (vreg->logical_type) {
1815 	case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1816 	case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1817 	case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1818 	case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1819 		ret = spmi_regulator_init_slew_rate(vreg);
1820 		if (ret)
1821 			return ret;
1822 		break;
1823 	case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426:
1824 		ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
1825 						SPMI_FTSMPS426_CLOCK_RATE);
1826 		if (ret)
1827 			return ret;
1828 		break;
1829 	case SPMI_REGULATOR_LOGICAL_TYPE_HFS430:
1830 		ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
1831 							SPMI_HFS430_CLOCK_RATE);
1832 		if (ret)
1833 			return ret;
1834 		break;
1835 	default:
1836 		break;
1837 	}
1838 
1839 	if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS)
1840 		vreg->ocp_irq = 0;
1841 
1842 	if (vreg->ocp_irq) {
1843 		ret = devm_request_irq(dev, vreg->ocp_irq,
1844 			spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp",
1845 			vreg);
1846 		if (ret < 0) {
1847 			dev_err(dev, "failed to request irq %d, ret=%d\n",
1848 				vreg->ocp_irq, ret);
1849 			return ret;
1850 		}
1851 
1852 		ret = devm_delayed_work_autocancel(dev, &vreg->ocp_work,
1853 						   spmi_regulator_vs_ocp_work);
1854 		if (ret)
1855 			return ret;
1856 	}
1857 
1858 	return 0;
1859 }
1860 
1861 static const struct spmi_regulator_data pm8941_regulators[] = {
1862 	{ "s1", 0x1400, "vdd_s1", },
1863 	{ "s2", 0x1700, "vdd_s2", },
1864 	{ "s3", 0x1a00, "vdd_s3", },
1865 	{ "s4", 0xa000, },
1866 	{ "l1", 0x4000, "vdd_l1_l3", },
1867 	{ "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
1868 	{ "l3", 0x4200, "vdd_l1_l3", },
1869 	{ "l4", 0x4300, "vdd_l4_l11", },
1870 	{ "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
1871 	{ "l6", 0x4500, "vdd_l6_l12_l14_l15", },
1872 	{ "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
1873 	{ "l8", 0x4700, "vdd_l8_l16_l18_19", },
1874 	{ "l9", 0x4800, "vdd_l9_l10_l17_l22", },
1875 	{ "l10", 0x4900, "vdd_l9_l10_l17_l22", },
1876 	{ "l11", 0x4a00, "vdd_l4_l11", },
1877 	{ "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
1878 	{ "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
1879 	{ "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
1880 	{ "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
1881 	{ "l16", 0x4f00, "vdd_l8_l16_l18_19", },
1882 	{ "l17", 0x5000, "vdd_l9_l10_l17_l22", },
1883 	{ "l18", 0x5100, "vdd_l8_l16_l18_19", },
1884 	{ "l19", 0x5200, "vdd_l8_l16_l18_19", },
1885 	{ "l20", 0x5300, "vdd_l13_l20_l23_l24", },
1886 	{ "l21", 0x5400, "vdd_l21", },
1887 	{ "l22", 0x5500, "vdd_l9_l10_l17_l22", },
1888 	{ "l23", 0x5600, "vdd_l13_l20_l23_l24", },
1889 	{ "l24", 0x5700, "vdd_l13_l20_l23_l24", },
1890 	{ "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
1891 	{ "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
1892 	{ "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
1893 	{ "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
1894 	{ "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
1895 	{ }
1896 };
1897 
1898 static const struct spmi_regulator_data pm8226_regulators[] = {
1899 	{ "s1", 0x1400, "vdd_s1", },
1900 	{ "s2", 0x1700, "vdd_s2", },
1901 	{ "s3", 0x1a00, "vdd_s3", },
1902 	{ "s4", 0x1d00, "vdd_s4", },
1903 	{ "s5", 0x2000, "vdd_s5", },
1904 	{ "l1", 0x4000, "vdd_l1_l2_l4_l5", },
1905 	{ "l2", 0x4100, "vdd_l1_l2_l4_l5", },
1906 	{ "l3", 0x4200, "vdd_l3_l24_l26", },
1907 	{ "l4", 0x4300, "vdd_l1_l2_l4_l5", },
1908 	{ "l5", 0x4400, "vdd_l1_l2_l4_l5", },
1909 	{ "l6", 0x4500, "vdd_l6_l7_l8_l9_l27", },
1910 	{ "l7", 0x4600, "vdd_l6_l7_l8_l9_l27", },
1911 	{ "l8", 0x4700, "vdd_l6_l7_l8_l9_l27", },
1912 	{ "l9", 0x4800, "vdd_l6_l7_l8_l9_l27", },
1913 	{ "l10", 0x4900, "vdd_l10_l11_l13", },
1914 	{ "l11", 0x4a00, "vdd_l10_l11_l13", },
1915 	{ "l12", 0x4b00, "vdd_l12_l14", },
1916 	{ "l13", 0x4c00, "vdd_l10_l11_l13", },
1917 	{ "l14", 0x4d00, "vdd_l12_l14", },
1918 	{ "l15", 0x4e00, "vdd_l15_l16_l17_l18", },
1919 	{ "l16", 0x4f00, "vdd_l15_l16_l17_l18", },
1920 	{ "l17", 0x5000, "vdd_l15_l16_l17_l18", },
1921 	{ "l18", 0x5100, "vdd_l15_l16_l17_l18", },
1922 	{ "l19", 0x5200, "vdd_l19_l20_l21_l22_l23_l28", },
1923 	{ "l20", 0x5300, "vdd_l19_l20_l21_l22_l23_l28", },
1924 	{ "l21", 0x5400, "vdd_l19_l20_l21_l22_l23_l28", },
1925 	{ "l22", 0x5500, "vdd_l19_l20_l21_l22_l23_l28", },
1926 	{ "l23", 0x5600, "vdd_l19_l20_l21_l22_l23_l28", },
1927 	{ "l24", 0x5700, "vdd_l3_l24_l26", },
1928 	{ "l25", 0x5800, "vdd_l25", },
1929 	{ "l26", 0x5900, "vdd_l3_l24_l26", },
1930 	{ "l27", 0x5a00, "vdd_l6_l7_l8_l9_l27", },
1931 	{ "l28", 0x5b00, "vdd_l19_l20_l21_l22_l23_l28", },
1932 	{ "lvs1", 0x8000, "vdd_lvs1", },
1933 	{ }
1934 };
1935 
1936 static const struct spmi_regulator_data pm8841_regulators[] = {
1937 	{ "s1", 0x1400, "vdd_s1", },
1938 	{ "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
1939 	{ "s3", 0x1a00, "vdd_s3", },
1940 	{ "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
1941 	{ "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
1942 	{ "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
1943 	{ "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
1944 	{ "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
1945 	{ }
1946 };
1947 
1948 static const struct spmi_regulator_data pm8916_regulators[] = {
1949 	{ "s1", 0x1400, "vdd_s1", },
1950 	{ "s2", 0x1700, "vdd_s2", },
1951 	{ "s3", 0x1a00, "vdd_s3", },
1952 	{ "s4", 0x1d00, "vdd_s4", },
1953 	{ "l1", 0x4000, "vdd_l1_l3", },
1954 	{ "l2", 0x4100, "vdd_l2", },
1955 	{ "l3", 0x4200, "vdd_l1_l3", },
1956 	{ "l4", 0x4300, "vdd_l4_l5_l6", },
1957 	{ "l5", 0x4400, "vdd_l4_l5_l6", },
1958 	{ "l6", 0x4500, "vdd_l4_l5_l6", },
1959 	{ "l7", 0x4600, "vdd_l7", },
1960 	{ "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
1961 	{ "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
1962 	{ "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
1963 	{ "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
1964 	{ "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
1965 	{ "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
1966 	{ "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
1967 	{ "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
1968 	{ "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
1969 	{ "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
1970 	{ "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
1971 	{ }
1972 };
1973 
1974 static const struct spmi_regulator_data pm8950_regulators[] = {
1975 	{ "s1", 0x1400, "vdd_s1", },
1976 	{ "s2", 0x1700, "vdd_s2", },
1977 	{ "s3", 0x1a00, "vdd_s3", },
1978 	{ "s4", 0x1d00, "vdd_s4", },
1979 	{ "s5", 0x2000, "vdd_s5", },
1980 	{ "s6", 0x2300, "vdd_s6", },
1981 	{ "l1", 0x4000, "vdd_l1_l19", },
1982 	{ "l2", 0x4100, "vdd_l2_l23", },
1983 	{ "l3", 0x4200, "vdd_l3", },
1984 	{ "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
1985 	{ "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
1986 	{ "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
1987 	{ "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
1988 	{ "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
1989 	{ "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
1990 	{ "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
1991 	{ "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
1992 	{ "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
1993 	{ "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
1994 	{ "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
1995 	{ "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
1996 	{ "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
1997 	{ "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
1998 	{ "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
1999 	{ "l19", 0x5200, "vdd_l1_l19", },
2000 	{ "l20", 0x5300, "vdd_l20", },
2001 	{ "l21", 0x5400, "vdd_l21", },
2002 	{ "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
2003 	{ "l23", 0x5600, "vdd_l2_l23", },
2004 	{ }
2005 };
2006 
2007 static const struct spmi_regulator_data pm8994_regulators[] = {
2008 	{ "s1", 0x1400, "vdd_s1", },
2009 	{ "s2", 0x1700, "vdd_s2", },
2010 	{ "s3", 0x1a00, "vdd_s3", },
2011 	{ "s4", 0x1d00, "vdd_s4", },
2012 	{ "s5", 0x2000, "vdd_s5", },
2013 	{ "s6", 0x2300, "vdd_s6", },
2014 	{ "s7", 0x2600, "vdd_s7", },
2015 	{ "s8", 0x2900, "vdd_s8", },
2016 	{ "s9", 0x2c00, "vdd_s9", },
2017 	{ "s10", 0x2f00, "vdd_s10", },
2018 	{ "s11", 0x3200, "vdd_s11", },
2019 	{ "s12", 0x3500, "vdd_s12", },
2020 	{ "l1", 0x4000, "vdd_l1", },
2021 	{ "l2", 0x4100, "vdd_l2_l26_l28", },
2022 	{ "l3", 0x4200, "vdd_l3_l11", },
2023 	{ "l4", 0x4300, "vdd_l4_l27_l31", },
2024 	{ "l5", 0x4400, "vdd_l5_l7", },
2025 	{ "l6", 0x4500, "vdd_l6_l12_l32", },
2026 	{ "l7", 0x4600, "vdd_l5_l7", },
2027 	{ "l8", 0x4700, "vdd_l8_l16_l30", },
2028 	{ "l9", 0x4800, "vdd_l9_l10_l18_l22", },
2029 	{ "l10", 0x4900, "vdd_l9_l10_l18_l22", },
2030 	{ "l11", 0x4a00, "vdd_l3_l11", },
2031 	{ "l12", 0x4b00, "vdd_l6_l12_l32", },
2032 	{ "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
2033 	{ "l14", 0x4d00, "vdd_l14_l15", },
2034 	{ "l15", 0x4e00, "vdd_l14_l15", },
2035 	{ "l16", 0x4f00, "vdd_l8_l16_l30", },
2036 	{ "l17", 0x5000, "vdd_l17_l29", },
2037 	{ "l18", 0x5100, "vdd_l9_l10_l18_l22", },
2038 	{ "l19", 0x5200, "vdd_l13_l19_l23_l24", },
2039 	{ "l20", 0x5300, "vdd_l20_l21", },
2040 	{ "l21", 0x5400, "vdd_l20_l21", },
2041 	{ "l22", 0x5500, "vdd_l9_l10_l18_l22", },
2042 	{ "l23", 0x5600, "vdd_l13_l19_l23_l24", },
2043 	{ "l24", 0x5700, "vdd_l13_l19_l23_l24", },
2044 	{ "l25", 0x5800, "vdd_l25", },
2045 	{ "l26", 0x5900, "vdd_l2_l26_l28", },
2046 	{ "l27", 0x5a00, "vdd_l4_l27_l31", },
2047 	{ "l28", 0x5b00, "vdd_l2_l26_l28", },
2048 	{ "l29", 0x5c00, "vdd_l17_l29", },
2049 	{ "l30", 0x5d00, "vdd_l8_l16_l30", },
2050 	{ "l31", 0x5e00, "vdd_l4_l27_l31", },
2051 	{ "l32", 0x5f00, "vdd_l6_l12_l32", },
2052 	{ "lvs1", 0x8000, "vdd_lvs_1_2", },
2053 	{ "lvs2", 0x8100, "vdd_lvs_1_2", },
2054 	{ }
2055 };
2056 
2057 static const struct spmi_regulator_data pmi8994_regulators[] = {
2058 	{ "s1", 0x1400, "vdd_s1", },
2059 	{ "s2", 0x1700, "vdd_s2", },
2060 	{ "s3", 0x1a00, "vdd_s3", },
2061 	{ "l1", 0x4000, "vdd_l1", },
2062 	{ }
2063 };
2064 
2065 static const struct spmi_regulator_data pm660_regulators[] = {
2066 	{ "s1", 0x1400, "vdd_s1", },
2067 	{ "s2", 0x1700, "vdd_s2", },
2068 	{ "s3", 0x1a00, "vdd_s3", },
2069 	{ "s4", 0x1d00, "vdd_s3", },
2070 	{ "s5", 0x2000, "vdd_s5", },
2071 	{ "s6", 0x2300, "vdd_s6", },
2072 	{ "l1", 0x4000, "vdd_l1_l6_l7", },
2073 	{ "l2", 0x4100, "vdd_l2_l3", },
2074 	{ "l3", 0x4200, "vdd_l2_l3", },
2075 	/* l4 is unaccessible on PM660 */
2076 	{ "l5", 0x4400, "vdd_l5", },
2077 	{ "l6", 0x4500, "vdd_l1_l6_l7", },
2078 	{ "l7", 0x4600, "vdd_l1_l6_l7", },
2079 	{ "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2080 	{ "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2081 	{ "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2082 	{ "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2083 	{ "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2084 	{ "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2085 	{ "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2086 	{ "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
2087 	{ "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
2088 	{ "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
2089 	{ "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
2090 	{ "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
2091 	{ }
2092 };
2093 
2094 static const struct spmi_regulator_data pm660l_regulators[] = {
2095 	{ "s1", 0x1400, "vdd_s1", },
2096 	{ "s2", 0x1700, "vdd_s2", },
2097 	{ "s3", 0x1a00, "vdd_s3", },
2098 	{ "s4", 0x1d00, "vdd_s4", },
2099 	{ "s5", 0x2000, "vdd_s5", },
2100 	{ "l1", 0x4000, "vdd_l1_l9_l10", },
2101 	{ "l2", 0x4100, "vdd_l2", },
2102 	{ "l3", 0x4200, "vdd_l3_l5_l7_l8", },
2103 	{ "l4", 0x4300, "vdd_l4_l6", },
2104 	{ "l5", 0x4400, "vdd_l3_l5_l7_l8", },
2105 	{ "l6", 0x4500, "vdd_l4_l6", },
2106 	{ "l7", 0x4600, "vdd_l3_l5_l7_l8", },
2107 	{ "l8", 0x4700, "vdd_l3_l5_l7_l8", },
2108 	{ "l9", 0x4800, "vdd_l1_l9_l10", },
2109 	{ "l10", 0x4900, "vdd_l1_l9_l10", },
2110 	{ }
2111 };
2112 
2113 
2114 static const struct spmi_regulator_data pm8004_regulators[] = {
2115 	{ "s2", 0x1700, "vdd_s2", },
2116 	{ "s5", 0x2000, "vdd_s5", },
2117 	{ }
2118 };
2119 
2120 static const struct spmi_regulator_data pm8005_regulators[] = {
2121 	{ "s1", 0x1400, "vdd_s1", },
2122 	{ "s2", 0x1700, "vdd_s2", },
2123 	{ "s3", 0x1a00, "vdd_s3", },
2124 	{ "s4", 0x1d00, "vdd_s4", },
2125 	{ }
2126 };
2127 
2128 static const struct spmi_regulator_data pms405_regulators[] = {
2129 	{ "s3", 0x1a00, "vdd_s3"},
2130 	{ }
2131 };
2132 
2133 static const struct of_device_id qcom_spmi_regulator_match[] = {
2134 	{ .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators },
2135 	{ .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators },
2136 	{ .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators },
2137 	{ .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators },
2138 	{ .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators },
2139 	{ .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators },
2140 	{ .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators },
2141 	{ .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators },
2142 	{ .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
2143 	{ .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
2144 	{ .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
2145 	{ .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
2146 	{ }
2147 };
2148 MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);
2149 
qcom_spmi_regulator_probe(struct platform_device * pdev)2150 static int qcom_spmi_regulator_probe(struct platform_device *pdev)
2151 {
2152 	const struct spmi_regulator_data *reg;
2153 	const struct spmi_voltage_range *range;
2154 	const struct of_device_id *match;
2155 	struct regulator_config config = { };
2156 	struct regulator_dev *rdev;
2157 	struct spmi_regulator *vreg;
2158 	struct regmap *regmap;
2159 	const char *name;
2160 	struct device *dev = &pdev->dev;
2161 	struct device_node *node = pdev->dev.of_node;
2162 	struct device_node *syscon, *reg_node;
2163 	struct property *reg_prop;
2164 	int ret, lenp;
2165 	struct list_head *vreg_list;
2166 
2167 	vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL);
2168 	if (!vreg_list)
2169 		return -ENOMEM;
2170 	INIT_LIST_HEAD(vreg_list);
2171 	platform_set_drvdata(pdev, vreg_list);
2172 
2173 	regmap = dev_get_regmap(dev->parent, NULL);
2174 	if (!regmap)
2175 		return -ENODEV;
2176 
2177 	match = of_match_device(qcom_spmi_regulator_match, &pdev->dev);
2178 	if (!match)
2179 		return -ENODEV;
2180 
2181 	if (of_find_property(node, "qcom,saw-reg", &lenp)) {
2182 		syscon = of_parse_phandle(node, "qcom,saw-reg", 0);
2183 		saw_regmap = syscon_node_to_regmap(syscon);
2184 		of_node_put(syscon);
2185 		if (IS_ERR(saw_regmap))
2186 			dev_err(dev, "ERROR reading SAW regmap\n");
2187 	}
2188 
2189 	for (reg = match->data; reg->name; reg++) {
2190 
2191 		if (saw_regmap) {
2192 			reg_node = of_get_child_by_name(node, reg->name);
2193 			reg_prop = of_find_property(reg_node, "qcom,saw-slave",
2194 						    &lenp);
2195 			of_node_put(reg_node);
2196 			if (reg_prop)
2197 				continue;
2198 		}
2199 
2200 		vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
2201 		if (!vreg)
2202 			return -ENOMEM;
2203 
2204 		vreg->dev = dev;
2205 		vreg->base = reg->base;
2206 		vreg->regmap = regmap;
2207 		if (reg->ocp) {
2208 			vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp);
2209 			if (vreg->ocp_irq < 0)
2210 				return vreg->ocp_irq;
2211 		}
2212 		vreg->desc.id = -1;
2213 		vreg->desc.owner = THIS_MODULE;
2214 		vreg->desc.type = REGULATOR_VOLTAGE;
2215 		vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE;
2216 		vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK;
2217 		vreg->desc.enable_val = SPMI_COMMON_ENABLE;
2218 		vreg->desc.name = name = reg->name;
2219 		vreg->desc.supply_name = reg->supply;
2220 		vreg->desc.of_match = reg->name;
2221 		vreg->desc.of_parse_cb = spmi_regulator_of_parse;
2222 		vreg->desc.of_map_mode = spmi_regulator_of_map_mode;
2223 
2224 		ret = spmi_regulator_match(vreg, reg->force_type);
2225 		if (ret)
2226 			continue;
2227 
2228 		if (saw_regmap) {
2229 			reg_node = of_get_child_by_name(node, reg->name);
2230 			reg_prop = of_find_property(reg_node, "qcom,saw-leader",
2231 						    &lenp);
2232 			of_node_put(reg_node);
2233 			if (reg_prop) {
2234 				spmi_saw_ops = *(vreg->desc.ops);
2235 				spmi_saw_ops.set_voltage_sel =
2236 					spmi_regulator_saw_set_voltage;
2237 				vreg->desc.ops = &spmi_saw_ops;
2238 			}
2239 		}
2240 
2241 		if (vreg->set_points && vreg->set_points->count == 1) {
2242 			/* since there is only one range */
2243 			range = vreg->set_points->range;
2244 			vreg->desc.uV_step = range->step_uV;
2245 		}
2246 
2247 		config.dev = dev;
2248 		config.driver_data = vreg;
2249 		config.regmap = regmap;
2250 		rdev = devm_regulator_register(dev, &vreg->desc, &config);
2251 		if (IS_ERR(rdev)) {
2252 			dev_err(dev, "failed to register %s\n", name);
2253 			return PTR_ERR(rdev);
2254 		}
2255 
2256 		INIT_LIST_HEAD(&vreg->node);
2257 		list_add(&vreg->node, vreg_list);
2258 	}
2259 
2260 	return 0;
2261 }
2262 
2263 static struct platform_driver qcom_spmi_regulator_driver = {
2264 	.driver		= {
2265 		.name	= "qcom-spmi-regulator",
2266 		.of_match_table = qcom_spmi_regulator_match,
2267 	},
2268 	.probe		= qcom_spmi_regulator_probe,
2269 };
2270 module_platform_driver(qcom_spmi_regulator_driver);
2271 
2272 MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver");
2273 MODULE_LICENSE("GPL v2");
2274 MODULE_ALIAS("platform:qcom-spmi-regulator");
2275