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Searched refs:R_IMR_MAILBOX_CLR_CPU (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/arch/mips/sibyte/sb1250/
Dsmp.c26 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
27 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
Dirq.c256 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); in arch_init_irq()
258 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); in arch_init_irq()
/linux-5.19.10/arch/mips/include/asm/sibyte/
Dsb1250_regs.h718 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 macro