1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _LINUX_QCOM_GENI_SE
7 #define _LINUX_QCOM_GENI_SE
8
9 #include <linux/interconnect.h>
10
11 /**
12 * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines
13 *
14 * @GENI_SE_INVALID: Invalid mode
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
16 * by programmed IO method
17 * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred
18 * with SE by DMAengine internal to SE
19 * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine
20 * configured by a firmware residing on a GSI engine. This DMA name is
21 * interchangeably used as GSI or GPI which seem to imply the same DMAengine
22 */
23
24 enum geni_se_xfer_mode {
25 GENI_SE_INVALID,
26 GENI_SE_FIFO,
27 GENI_SE_DMA,
28 GENI_GPI_DMA,
29 };
30
31 /* Protocols supported by GENI Serial Engines */
32 enum geni_se_protocol_type {
33 GENI_SE_NONE,
34 GENI_SE_SPI,
35 GENI_SE_UART,
36 GENI_SE_I2C,
37 GENI_SE_I3C,
38 };
39
40 struct geni_wrapper;
41 struct clk;
42
43 enum geni_icc_path_index {
44 GENI_TO_CORE,
45 CPU_TO_GENI,
46 GENI_TO_DDR
47 };
48
49 struct geni_icc_path {
50 struct icc_path *path;
51 unsigned int avg_bw;
52 };
53
54 /**
55 * struct geni_se - GENI Serial Engine
56 * @base: Base Address of the Serial Engine's register block
57 * @dev: Pointer to the Serial Engine device
58 * @wrapper: Pointer to the parent QUP Wrapper core
59 * @clk: Handle to the core serial engine clock
60 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl
61 * @clk_perf_tbl: Table of clock frequency input to serial engine clock
62 * @icc_paths: Array of ICC paths for SE
63 */
64 struct geni_se {
65 void __iomem *base;
66 struct device *dev;
67 struct geni_wrapper *wrapper;
68 struct clk *clk;
69 unsigned int num_clk_levels;
70 unsigned long *clk_perf_tbl;
71 struct geni_icc_path icc_paths[3];
72 };
73
74 /* Common SE registers */
75 #define GENI_FORCE_DEFAULT_REG 0x20
76 #define SE_GENI_STATUS 0x40
77 #define GENI_SER_M_CLK_CFG 0x48
78 #define GENI_SER_S_CLK_CFG 0x4c
79 #define GENI_IF_DISABLE_RO 0x64
80 #define GENI_FW_REVISION_RO 0x68
81 #define SE_GENI_CLK_SEL 0x7c
82 #define SE_GENI_DMA_MODE_EN 0x258
83 #define SE_GENI_M_CMD0 0x600
84 #define SE_GENI_M_CMD_CTRL_REG 0x604
85 #define SE_GENI_M_IRQ_STATUS 0x610
86 #define SE_GENI_M_IRQ_EN 0x614
87 #define SE_GENI_M_IRQ_CLEAR 0x618
88 #define SE_GENI_S_CMD0 0x630
89 #define SE_GENI_S_CMD_CTRL_REG 0x634
90 #define SE_GENI_S_IRQ_STATUS 0x640
91 #define SE_GENI_S_IRQ_EN 0x644
92 #define SE_GENI_S_IRQ_CLEAR 0x648
93 #define SE_GENI_TX_FIFOn 0x700
94 #define SE_GENI_RX_FIFOn 0x780
95 #define SE_GENI_TX_FIFO_STATUS 0x800
96 #define SE_GENI_RX_FIFO_STATUS 0x804
97 #define SE_GENI_TX_WATERMARK_REG 0x80c
98 #define SE_GENI_RX_WATERMARK_REG 0x810
99 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814
100 #define SE_GENI_IOS 0x908
101 #define SE_DMA_TX_IRQ_STAT 0xc40
102 #define SE_DMA_TX_IRQ_CLR 0xc44
103 #define SE_DMA_TX_FSM_RST 0xc58
104 #define SE_DMA_RX_IRQ_STAT 0xd40
105 #define SE_DMA_RX_IRQ_CLR 0xd44
106 #define SE_DMA_RX_FSM_RST 0xd58
107 #define SE_HW_PARAM_0 0xe24
108 #define SE_HW_PARAM_1 0xe28
109
110 /* GENI_FORCE_DEFAULT_REG fields */
111 #define FORCE_DEFAULT BIT(0)
112
113 /* GENI_STATUS fields */
114 #define M_GENI_CMD_ACTIVE BIT(0)
115 #define S_GENI_CMD_ACTIVE BIT(12)
116
117 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
118 #define SER_CLK_EN BIT(0)
119 #define CLK_DIV_MSK GENMASK(15, 4)
120 #define CLK_DIV_SHFT 4
121
122 /* GENI_IF_DISABLE_RO fields */
123 #define FIFO_IF_DISABLE (BIT(0))
124
125 /* GENI_FW_REVISION_RO fields */
126 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
127 #define FW_REV_PROTOCOL_SHFT 8
128
129 /* GENI_CLK_SEL fields */
130 #define CLK_SEL_MSK GENMASK(2, 0)
131
132 /* SE_GENI_DMA_MODE_EN */
133 #define GENI_DMA_MODE_EN BIT(0)
134
135 /* GENI_M_CMD0 fields */
136 #define M_OPCODE_MSK GENMASK(31, 27)
137 #define M_OPCODE_SHFT 27
138 #define M_PARAMS_MSK GENMASK(26, 0)
139
140 /* GENI_M_CMD_CTRL_REG */
141 #define M_GENI_CMD_CANCEL BIT(2)
142 #define M_GENI_CMD_ABORT BIT(1)
143 #define M_GENI_DISABLE BIT(0)
144
145 /* GENI_S_CMD0 fields */
146 #define S_OPCODE_MSK GENMASK(31, 27)
147 #define S_OPCODE_SHFT 27
148 #define S_PARAMS_MSK GENMASK(26, 0)
149
150 /* GENI_S_CMD_CTRL_REG */
151 #define S_GENI_CMD_CANCEL BIT(2)
152 #define S_GENI_CMD_ABORT BIT(1)
153 #define S_GENI_DISABLE BIT(0)
154
155 /* GENI_M_IRQ_EN fields */
156 #define M_CMD_DONE_EN BIT(0)
157 #define M_CMD_OVERRUN_EN BIT(1)
158 #define M_ILLEGAL_CMD_EN BIT(2)
159 #define M_CMD_FAILURE_EN BIT(3)
160 #define M_CMD_CANCEL_EN BIT(4)
161 #define M_CMD_ABORT_EN BIT(5)
162 #define M_TIMESTAMP_EN BIT(6)
163 #define M_RX_IRQ_EN BIT(7)
164 #define M_GP_SYNC_IRQ_0_EN BIT(8)
165 #define M_GP_IRQ_0_EN BIT(9)
166 #define M_GP_IRQ_1_EN BIT(10)
167 #define M_GP_IRQ_2_EN BIT(11)
168 #define M_GP_IRQ_3_EN BIT(12)
169 #define M_GP_IRQ_4_EN BIT(13)
170 #define M_GP_IRQ_5_EN BIT(14)
171 #define M_IO_DATA_DEASSERT_EN BIT(22)
172 #define M_IO_DATA_ASSERT_EN BIT(23)
173 #define M_RX_FIFO_RD_ERR_EN BIT(24)
174 #define M_RX_FIFO_WR_ERR_EN BIT(25)
175 #define M_RX_FIFO_WATERMARK_EN BIT(26)
176 #define M_RX_FIFO_LAST_EN BIT(27)
177 #define M_TX_FIFO_RD_ERR_EN BIT(28)
178 #define M_TX_FIFO_WR_ERR_EN BIT(29)
179 #define M_TX_FIFO_WATERMARK_EN BIT(30)
180 #define M_SEC_IRQ_EN BIT(31)
181 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
182 M_IO_DATA_DEASSERT_EN | \
183 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
184 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
185 M_TX_FIFO_WR_ERR_EN)
186
187 /* GENI_S_IRQ_EN fields */
188 #define S_CMD_DONE_EN BIT(0)
189 #define S_CMD_OVERRUN_EN BIT(1)
190 #define S_ILLEGAL_CMD_EN BIT(2)
191 #define S_CMD_FAILURE_EN BIT(3)
192 #define S_CMD_CANCEL_EN BIT(4)
193 #define S_CMD_ABORT_EN BIT(5)
194 #define S_GP_SYNC_IRQ_0_EN BIT(8)
195 #define S_GP_IRQ_0_EN BIT(9)
196 #define S_GP_IRQ_1_EN BIT(10)
197 #define S_GP_IRQ_2_EN BIT(11)
198 #define S_GP_IRQ_3_EN BIT(12)
199 #define S_GP_IRQ_4_EN BIT(13)
200 #define S_GP_IRQ_5_EN BIT(14)
201 #define S_IO_DATA_DEASSERT_EN BIT(22)
202 #define S_IO_DATA_ASSERT_EN BIT(23)
203 #define S_RX_FIFO_RD_ERR_EN BIT(24)
204 #define S_RX_FIFO_WR_ERR_EN BIT(25)
205 #define S_RX_FIFO_WATERMARK_EN BIT(26)
206 #define S_RX_FIFO_LAST_EN BIT(27)
207 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
208 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
209
210 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
211 #define WATERMARK_MSK GENMASK(5, 0)
212
213 /* GENI_TX_FIFO_STATUS fields */
214 #define TX_FIFO_WC GENMASK(27, 0)
215
216 /* GENI_RX_FIFO_STATUS fields */
217 #define RX_LAST BIT(31)
218 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
219 #define RX_LAST_BYTE_VALID_SHFT 28
220 #define RX_FIFO_WC_MSK GENMASK(24, 0)
221
222 /* SE_GENI_IOS fields */
223 #define IO2_DATA_IN BIT(1)
224 #define RX_DATA_IN BIT(0)
225
226 /* SE_DMA_TX_IRQ_STAT Register fields */
227 #define TX_DMA_DONE BIT(0)
228 #define TX_EOT BIT(1)
229 #define TX_SBE BIT(2)
230 #define TX_RESET_DONE BIT(3)
231
232 /* SE_DMA_RX_IRQ_STAT Register fields */
233 #define RX_DMA_DONE BIT(0)
234 #define RX_EOT BIT(1)
235 #define RX_SBE BIT(2)
236 #define RX_RESET_DONE BIT(3)
237 #define RX_FLUSH_DONE BIT(4)
238 #define RX_GENI_GP_IRQ GENMASK(10, 5)
239 #define RX_GENI_CANCEL_IRQ BIT(11)
240 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
241
242 /* SE_HW_PARAM_0 fields */
243 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
244 #define TX_FIFO_WIDTH_SHFT 24
245 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
246 #define TX_FIFO_DEPTH_SHFT 16
247
248 /* SE_HW_PARAM_1 fields */
249 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
250 #define RX_FIFO_WIDTH_SHFT 24
251 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
252 #define RX_FIFO_DEPTH_SHFT 16
253
254 #define HW_VER_MAJOR_MASK GENMASK(31, 28)
255 #define HW_VER_MAJOR_SHFT 28
256 #define HW_VER_MINOR_MASK GENMASK(27, 16)
257 #define HW_VER_MINOR_SHFT 16
258 #define HW_VER_STEP_MASK GENMASK(15, 0)
259
260 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
261 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
262 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
263
264 /* QUP SE VERSION value for major number 2 and minor number 5 */
265 #define QUP_SE_VERSION_2_5 0x20050000
266
267 /*
268 * Define bandwidth thresholds that cause the underlying Core 2X interconnect
269 * clock to run at the named frequency. These baseline values are recommended
270 * by the hardware team, and are not dynamically scaled with GENI bandwidth
271 * beyond basic on/off.
272 */
273 #define CORE_2X_19_2_MHZ 960
274 #define CORE_2X_50_MHZ 2500
275 #define CORE_2X_100_MHZ 5000
276 #define CORE_2X_150_MHZ 7500
277 #define CORE_2X_200_MHZ 10000
278 #define CORE_2X_236_MHZ 16383
279
280 #define GENI_DEFAULT_BW Bps_to_icc(1000)
281
282 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
283
284 u32 geni_se_get_qup_hw_version(struct geni_se *se);
285
286 /**
287 * geni_se_read_proto() - Read the protocol configured for a serial engine
288 * @se: Pointer to the concerned serial engine.
289 *
290 * Return: Protocol value as configured in the serial engine.
291 */
geni_se_read_proto(struct geni_se * se)292 static inline u32 geni_se_read_proto(struct geni_se *se)
293 {
294 u32 val;
295
296 val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
297
298 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
299 }
300
301 /**
302 * geni_se_setup_m_cmd() - Setup the primary sequencer
303 * @se: Pointer to the concerned serial engine.
304 * @cmd: Command/Operation to setup in the primary sequencer.
305 * @params: Parameter for the sequencer command.
306 *
307 * This function is used to configure the primary sequencer with the
308 * command and its associated parameters.
309 */
geni_se_setup_m_cmd(struct geni_se * se,u32 cmd,u32 params)310 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
311 {
312 u32 m_cmd;
313
314 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
315 writel(m_cmd, se->base + SE_GENI_M_CMD0);
316 }
317
318 /**
319 * geni_se_setup_s_cmd() - Setup the secondary sequencer
320 * @se: Pointer to the concerned serial engine.
321 * @cmd: Command/Operation to setup in the secondary sequencer.
322 * @params: Parameter for the sequencer command.
323 *
324 * This function is used to configure the secondary sequencer with the
325 * command and its associated parameters.
326 */
geni_se_setup_s_cmd(struct geni_se * se,u32 cmd,u32 params)327 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
328 {
329 u32 s_cmd;
330
331 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
332 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
333 s_cmd |= (cmd << S_OPCODE_SHFT);
334 s_cmd |= (params & S_PARAMS_MSK);
335 writel(s_cmd, se->base + SE_GENI_S_CMD0);
336 }
337
338 /**
339 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary
340 * sequencer
341 * @se: Pointer to the concerned serial engine.
342 *
343 * This function is used to cancel the currently configured command in the
344 * primary sequencer.
345 */
geni_se_cancel_m_cmd(struct geni_se * se)346 static inline void geni_se_cancel_m_cmd(struct geni_se *se)
347 {
348 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
349 }
350
351 /**
352 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
353 * sequencer
354 * @se: Pointer to the concerned serial engine.
355 *
356 * This function is used to cancel the currently configured command in the
357 * secondary sequencer.
358 */
geni_se_cancel_s_cmd(struct geni_se * se)359 static inline void geni_se_cancel_s_cmd(struct geni_se *se)
360 {
361 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
362 }
363
364 /**
365 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
366 * @se: Pointer to the concerned serial engine.
367 *
368 * This function is used to force abort the currently configured command in the
369 * primary sequencer.
370 */
geni_se_abort_m_cmd(struct geni_se * se)371 static inline void geni_se_abort_m_cmd(struct geni_se *se)
372 {
373 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
374 }
375
376 /**
377 * geni_se_abort_s_cmd() - Abort the command configured in the secondary
378 * sequencer
379 * @se: Pointer to the concerned serial engine.
380 *
381 * This function is used to force abort the currently configured command in the
382 * secondary sequencer.
383 */
geni_se_abort_s_cmd(struct geni_se * se)384 static inline void geni_se_abort_s_cmd(struct geni_se *se)
385 {
386 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
387 }
388
389 /**
390 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
391 * @se: Pointer to the concerned serial engine.
392 *
393 * This function is used to get the depth i.e. number of elements in the
394 * TX fifo of the serial engine.
395 *
396 * Return: TX fifo depth in units of FIFO words.
397 */
geni_se_get_tx_fifo_depth(struct geni_se * se)398 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
399 {
400 u32 val;
401
402 val = readl_relaxed(se->base + SE_HW_PARAM_0);
403
404 return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
405 }
406
407 /**
408 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
409 * @se: Pointer to the concerned serial engine.
410 *
411 * This function is used to get the width i.e. word size per element in the
412 * TX fifo of the serial engine.
413 *
414 * Return: TX fifo width in bits
415 */
geni_se_get_tx_fifo_width(struct geni_se * se)416 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
417 {
418 u32 val;
419
420 val = readl_relaxed(se->base + SE_HW_PARAM_0);
421
422 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
423 }
424
425 /**
426 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
427 * @se: Pointer to the concerned serial engine.
428 *
429 * This function is used to get the depth i.e. number of elements in the
430 * RX fifo of the serial engine.
431 *
432 * Return: RX fifo depth in units of FIFO words
433 */
geni_se_get_rx_fifo_depth(struct geni_se * se)434 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
435 {
436 u32 val;
437
438 val = readl_relaxed(se->base + SE_HW_PARAM_1);
439
440 return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
441 }
442
443 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
444
445 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
446
447 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
448 bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
449
450 int geni_se_resources_off(struct geni_se *se);
451
452 int geni_se_resources_on(struct geni_se *se);
453
454 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
455
456 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
457 unsigned int *index, unsigned long *res_freq,
458 bool exact);
459
460 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
461 dma_addr_t *iova);
462
463 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
464 dma_addr_t *iova);
465
466 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
467
468 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
469
470 int geni_icc_get(struct geni_se *se, const char *icc_ddr);
471
472 int geni_icc_set_bw(struct geni_se *se);
473 void geni_icc_set_tag(struct geni_se *se, u32 tag);
474
475 int geni_icc_enable(struct geni_se *se);
476
477 int geni_icc_disable(struct geni_se *se);
478 #endif
479 #endif
480