1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7 
8 #include "core.h"
9 
10 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
11 #define ADDR_CAM_ENT_SIZE  0x40
12 #define BSSID_CAM_ENT_SIZE 0x08
13 #define HFC_PAGE_UNIT 64
14 
15 enum rtw89_mac_hwmod_sel {
16 	RTW89_DMAC_SEL = 0,
17 	RTW89_CMAC_SEL = 1,
18 
19 	RTW89_MAC_INVALID,
20 };
21 
22 enum rtw89_mac_fwd_target {
23 	RTW89_FWD_DONT_CARE    = 0,
24 	RTW89_FWD_TO_HOST      = 1,
25 	RTW89_FWD_TO_WLAN_CPU  = 2
26 };
27 
28 enum rtw89_mac_wd_dma_intvl {
29 	RTW89_MAC_WD_DMA_INTVL_0S,
30 	RTW89_MAC_WD_DMA_INTVL_256NS,
31 	RTW89_MAC_WD_DMA_INTVL_512NS,
32 	RTW89_MAC_WD_DMA_INTVL_768NS,
33 	RTW89_MAC_WD_DMA_INTVL_1US,
34 	RTW89_MAC_WD_DMA_INTVL_1_5US,
35 	RTW89_MAC_WD_DMA_INTVL_2US,
36 	RTW89_MAC_WD_DMA_INTVL_4US,
37 	RTW89_MAC_WD_DMA_INTVL_8US,
38 	RTW89_MAC_WD_DMA_INTVL_16US,
39 	RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
40 };
41 
42 enum rtw89_mac_multi_tag_num {
43 	RTW89_MAC_TAG_NUM_1,
44 	RTW89_MAC_TAG_NUM_2,
45 	RTW89_MAC_TAG_NUM_3,
46 	RTW89_MAC_TAG_NUM_4,
47 	RTW89_MAC_TAG_NUM_5,
48 	RTW89_MAC_TAG_NUM_6,
49 	RTW89_MAC_TAG_NUM_7,
50 	RTW89_MAC_TAG_NUM_8,
51 	RTW89_MAC_TAG_NUM_DEF = 0xFE
52 };
53 
54 enum rtw89_mac_lbc_tmr {
55 	RTW89_MAC_LBC_TMR_8US = 0,
56 	RTW89_MAC_LBC_TMR_16US,
57 	RTW89_MAC_LBC_TMR_32US,
58 	RTW89_MAC_LBC_TMR_64US,
59 	RTW89_MAC_LBC_TMR_128US,
60 	RTW89_MAC_LBC_TMR_256US,
61 	RTW89_MAC_LBC_TMR_512US,
62 	RTW89_MAC_LBC_TMR_1MS,
63 	RTW89_MAC_LBC_TMR_2MS,
64 	RTW89_MAC_LBC_TMR_4MS,
65 	RTW89_MAC_LBC_TMR_8MS,
66 	RTW89_MAC_LBC_TMR_DEF = 0xFE
67 };
68 
69 enum rtw89_mac_cpuio_op_cmd_type {
70 	CPUIO_OP_CMD_GET_1ST_PID = 0,
71 	CPUIO_OP_CMD_GET_NEXT_PID = 1,
72 	CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
73 	CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
74 	CPUIO_OP_CMD_DEQ = 8,
75 	CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
76 	CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
77 };
78 
79 enum rtw89_mac_wde_dle_port_id {
80 	WDE_DLE_PORT_ID_DISPATCH = 0,
81 	WDE_DLE_PORT_ID_PKTIN = 1,
82 	WDE_DLE_PORT_ID_CMAC0 = 3,
83 	WDE_DLE_PORT_ID_CMAC1 = 4,
84 	WDE_DLE_PORT_ID_CPU_IO = 6,
85 	WDE_DLE_PORT_ID_WDRLS = 7,
86 	WDE_DLE_PORT_ID_END = 8
87 };
88 
89 enum rtw89_mac_wde_dle_queid_wdrls {
90 	WDE_DLE_QUEID_TXOK = 0,
91 	WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
92 	WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
93 	WDE_DLE_QUEID_DROP_MACID_DROP = 3,
94 	WDE_DLE_QUEID_NO_REPORT = 4
95 };
96 
97 enum rtw89_mac_ple_dle_port_id {
98 	PLE_DLE_PORT_ID_DISPATCH = 0,
99 	PLE_DLE_PORT_ID_MPDU = 1,
100 	PLE_DLE_PORT_ID_SEC = 2,
101 	PLE_DLE_PORT_ID_CMAC0 = 3,
102 	PLE_DLE_PORT_ID_CMAC1 = 4,
103 	PLE_DLE_PORT_ID_WDRLS = 5,
104 	PLE_DLE_PORT_ID_CPU_IO = 6,
105 	PLE_DLE_PORT_ID_PLRLS = 7,
106 	PLE_DLE_PORT_ID_END = 8
107 };
108 
109 enum rtw89_mac_ple_dle_queid_plrls {
110 	PLE_DLE_QUEID_NO_REPORT = 0x0
111 };
112 
113 enum rtw89_machdr_frame_type {
114 	RTW89_MGNT = 0,
115 	RTW89_CTRL = 1,
116 	RTW89_DATA = 2,
117 };
118 
119 enum rtw89_mac_dle_dfi_type {
120 	DLE_DFI_TYPE_FREEPG	= 0,
121 	DLE_DFI_TYPE_QUOTA	= 1,
122 	DLE_DFI_TYPE_PAGELLT	= 2,
123 	DLE_DFI_TYPE_PKTINFO	= 3,
124 	DLE_DFI_TYPE_PREPKTLLT	= 4,
125 	DLE_DFI_TYPE_NXTPKTLLT	= 5,
126 	DLE_DFI_TYPE_QLNKTBL	= 6,
127 	DLE_DFI_TYPE_QEMPTY	= 7,
128 };
129 
130 enum rtw89_mac_dle_wde_quota_id {
131 	WDE_QTAID_HOST_IF = 0,
132 	WDE_QTAID_WLAN_CPU = 1,
133 	WDE_QTAID_DATA_CPU = 2,
134 	WDE_QTAID_PKTIN = 3,
135 	WDE_QTAID_CPUIO = 4,
136 };
137 
138 enum rtw89_mac_dle_ple_quota_id {
139 	PLE_QTAID_B0_TXPL = 0,
140 	PLE_QTAID_B1_TXPL = 1,
141 	PLE_QTAID_C2H = 2,
142 	PLE_QTAID_H2C = 3,
143 	PLE_QTAID_WLAN_CPU = 4,
144 	PLE_QTAID_MPDU = 5,
145 	PLE_QTAID_CMAC0_RX = 6,
146 	PLE_QTAID_CMAC1_RX = 7,
147 	PLE_QTAID_CMAC1_BBRPT = 8,
148 	PLE_QTAID_WDRLS = 9,
149 	PLE_QTAID_CPUIO = 10,
150 };
151 
152 enum rtw89_mac_dle_ctrl_type {
153 	DLE_CTRL_TYPE_WDE = 0,
154 	DLE_CTRL_TYPE_PLE = 1,
155 	DLE_CTRL_TYPE_NUM = 2,
156 };
157 
158 enum rtw89_mac_ax_l0_to_l1_event {
159 	MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
160 	MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
161 	MAC_AX_L0_TO_L1_RLS_PKID = 2,
162 	MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
163 	MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
164 	MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
165 	MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
166 	MAC_AX_L0_TO_L1_EVENT_MAX = 15,
167 };
168 
169 enum rtw89_mac_dbg_port_sel {
170 	/* CMAC 0 related */
171 	RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
172 	RTW89_DBG_PORT_SEL_SCH_C0,
173 	RTW89_DBG_PORT_SEL_TMAC_C0,
174 	RTW89_DBG_PORT_SEL_RMAC_C0,
175 	RTW89_DBG_PORT_SEL_RMACST_C0,
176 	RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
177 	RTW89_DBG_PORT_SEL_TRXPTCL_C0,
178 	RTW89_DBG_PORT_SEL_TX_INFOL_C0,
179 	RTW89_DBG_PORT_SEL_TX_INFOH_C0,
180 	RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
181 	RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
182 	/* CMAC 1 related */
183 	RTW89_DBG_PORT_SEL_PTCL_C1,
184 	RTW89_DBG_PORT_SEL_SCH_C1,
185 	RTW89_DBG_PORT_SEL_TMAC_C1,
186 	RTW89_DBG_PORT_SEL_RMAC_C1,
187 	RTW89_DBG_PORT_SEL_RMACST_C1,
188 	RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
189 	RTW89_DBG_PORT_SEL_TRXPTCL_C1,
190 	RTW89_DBG_PORT_SEL_TX_INFOL_C1,
191 	RTW89_DBG_PORT_SEL_TX_INFOH_C1,
192 	RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
193 	RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
194 	/* DLE related */
195 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
196 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
197 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
198 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
199 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
200 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
201 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
202 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
203 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
204 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
205 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
206 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
207 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
208 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
209 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
210 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
211 	RTW89_DBG_PORT_SEL_PKTINFO,
212 	/* PCIE related */
213 	RTW89_DBG_PORT_SEL_PCIE_TXDMA,
214 	RTW89_DBG_PORT_SEL_PCIE_RXDMA,
215 	RTW89_DBG_PORT_SEL_PCIE_CVT,
216 	RTW89_DBG_PORT_SEL_PCIE_CXPL,
217 	RTW89_DBG_PORT_SEL_PCIE_IO,
218 	RTW89_DBG_PORT_SEL_PCIE_MISC,
219 	RTW89_DBG_PORT_SEL_PCIE_MISC2,
220 
221 	/* keep last */
222 	RTW89_DBG_PORT_SEL_LAST,
223 	RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
224 	RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
225 };
226 
227 /* SRAM mem dump */
228 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
229 
230 #define	AXIDMA_BASE_ADDR		0x18006000
231 #define	STA_SCHED_BASE_ADDR		0x18808000
232 #define	RXPLD_FLTR_CAM_BASE_ADDR	0x18813000
233 #define	SECURITY_CAM_BASE_ADDR		0x18814000
234 #define	WOW_CAM_BASE_ADDR		0x18815000
235 #define	CMAC_TBL_BASE_ADDR		0x18840000
236 #define	ADDR_CAM_BASE_ADDR		0x18850000
237 #define	BSSID_CAM_BASE_ADDR		0x18853000
238 #define	BA_CAM_BASE_ADDR		0x18854000
239 #define	BCN_IE_CAM0_BASE_ADDR		0x18855000
240 #define	SHARED_BUF_BASE_ADDR		0x18700000
241 #define	DMAC_TBL_BASE_ADDR		0x18800000
242 #define	SHCUT_MACHDR_BASE_ADDR		0x18800800
243 #define	BCN_IE_CAM1_BASE_ADDR		0x188A0000
244 #define	TXD_FIFO_0_BASE_ADDR		0x18856200
245 #define	TXD_FIFO_1_BASE_ADDR		0x188A1080
246 #define	TXDATA_FIFO_0_BASE_ADDR		0x18856000
247 #define	TXDATA_FIFO_1_BASE_ADDR		0x188A1000
248 #define	CPU_LOCAL_BASE_ADDR		0x18003000
249 
250 #define CCTL_INFO_SIZE		32
251 
252 enum rtw89_mac_mem_sel {
253 	RTW89_MAC_MEM_AXIDMA,
254 	RTW89_MAC_MEM_SHARED_BUF,
255 	RTW89_MAC_MEM_DMAC_TBL,
256 	RTW89_MAC_MEM_SHCUT_MACHDR,
257 	RTW89_MAC_MEM_STA_SCHED,
258 	RTW89_MAC_MEM_RXPLD_FLTR_CAM,
259 	RTW89_MAC_MEM_SECURITY_CAM,
260 	RTW89_MAC_MEM_WOW_CAM,
261 	RTW89_MAC_MEM_CMAC_TBL,
262 	RTW89_MAC_MEM_ADDR_CAM,
263 	RTW89_MAC_MEM_BA_CAM,
264 	RTW89_MAC_MEM_BCN_IE_CAM0,
265 	RTW89_MAC_MEM_BCN_IE_CAM1,
266 	RTW89_MAC_MEM_TXD_FIFO_0,
267 	RTW89_MAC_MEM_TXD_FIFO_1,
268 	RTW89_MAC_MEM_TXDATA_FIFO_0,
269 	RTW89_MAC_MEM_TXDATA_FIFO_1,
270 	RTW89_MAC_MEM_CPU_LOCAL,
271 	RTW89_MAC_MEM_BSSID_CAM,
272 
273 	/* keep last */
274 	RTW89_MAC_MEM_NUM,
275 };
276 
277 extern const u32 rtw89_mac_mem_base_addrs[];
278 
279 enum rtw89_rpwm_req_pwr_state {
280 	RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
281 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
282 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
283 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
284 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
285 	RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
286 	RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
287 	RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
288 	RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
289 };
290 
291 struct rtw89_pwr_cfg {
292 	u16 addr;
293 	u8 cv_msk;
294 	u8 intf_msk;
295 	u8 base:4;
296 	u8 cmd:4;
297 	u8 msk;
298 	u8 val;
299 };
300 
301 enum rtw89_mac_c2h_ofld_func {
302 	RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
303 	RTW89_MAC_C2H_FUNC_READ_RSP,
304 	RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
305 	RTW89_MAC_C2H_FUNC_BCN_RESEND,
306 	RTW89_MAC_C2H_FUNC_MACID_PAUSE,
307 	RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
308 	RTW89_MAC_C2H_FUNC_OFLD_MAX,
309 };
310 
311 enum rtw89_mac_c2h_info_func {
312 	RTW89_MAC_C2H_FUNC_REC_ACK,
313 	RTW89_MAC_C2H_FUNC_DONE_ACK,
314 	RTW89_MAC_C2H_FUNC_C2H_LOG,
315 	RTW89_MAC_C2H_FUNC_BCN_CNT,
316 	RTW89_MAC_C2H_FUNC_INFO_MAX,
317 };
318 
319 enum rtw89_mac_c2h_class {
320 	RTW89_MAC_C2H_CLASS_INFO,
321 	RTW89_MAC_C2H_CLASS_OFLD,
322 	RTW89_MAC_C2H_CLASS_TWT,
323 	RTW89_MAC_C2H_CLASS_WOW,
324 	RTW89_MAC_C2H_CLASS_MCC,
325 	RTW89_MAC_C2H_CLASS_FWDBG,
326 	RTW89_MAC_C2H_CLASS_MAX,
327 };
328 
329 struct rtw89_mac_ax_coex {
330 #define RTW89_MAC_AX_COEX_RTK_MODE 0
331 #define RTW89_MAC_AX_COEX_CSR_MODE 1
332 	u8 pta_mode;
333 #define RTW89_MAC_AX_COEX_INNER 0
334 #define RTW89_MAC_AX_COEX_OUTPUT 1
335 #define RTW89_MAC_AX_COEX_INPUT 2
336 	u8 direction;
337 };
338 
339 struct rtw89_mac_ax_plt {
340 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
341 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
342 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
343 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
344 	u8 band;
345 	u8 tx;
346 	u8 rx;
347 };
348 
349 enum rtw89_mac_bf_rrsc_rate {
350 	RTW89_MAC_BF_RRSC_6M = 0,
351 	RTW89_MAC_BF_RRSC_9M = 1,
352 	RTW89_MAC_BF_RRSC_12M,
353 	RTW89_MAC_BF_RRSC_18M,
354 	RTW89_MAC_BF_RRSC_24M,
355 	RTW89_MAC_BF_RRSC_36M,
356 	RTW89_MAC_BF_RRSC_48M,
357 	RTW89_MAC_BF_RRSC_54M,
358 	RTW89_MAC_BF_RRSC_HT_MSC0,
359 	RTW89_MAC_BF_RRSC_HT_MSC1,
360 	RTW89_MAC_BF_RRSC_HT_MSC2,
361 	RTW89_MAC_BF_RRSC_HT_MSC3,
362 	RTW89_MAC_BF_RRSC_HT_MSC4,
363 	RTW89_MAC_BF_RRSC_HT_MSC5,
364 	RTW89_MAC_BF_RRSC_HT_MSC6,
365 	RTW89_MAC_BF_RRSC_HT_MSC7,
366 	RTW89_MAC_BF_RRSC_VHT_MSC0,
367 	RTW89_MAC_BF_RRSC_VHT_MSC1,
368 	RTW89_MAC_BF_RRSC_VHT_MSC2,
369 	RTW89_MAC_BF_RRSC_VHT_MSC3,
370 	RTW89_MAC_BF_RRSC_VHT_MSC4,
371 	RTW89_MAC_BF_RRSC_VHT_MSC5,
372 	RTW89_MAC_BF_RRSC_VHT_MSC6,
373 	RTW89_MAC_BF_RRSC_VHT_MSC7,
374 	RTW89_MAC_BF_RRSC_HE_MSC0,
375 	RTW89_MAC_BF_RRSC_HE_MSC1,
376 	RTW89_MAC_BF_RRSC_HE_MSC2,
377 	RTW89_MAC_BF_RRSC_HE_MSC3,
378 	RTW89_MAC_BF_RRSC_HE_MSC4,
379 	RTW89_MAC_BF_RRSC_HE_MSC5,
380 	RTW89_MAC_BF_RRSC_HE_MSC6,
381 	RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
382 	RTW89_MAC_BF_RRSC_MAX = 32
383 };
384 
385 #define RTW89_R32_EA		0xEAEAEAEA
386 #define RTW89_R32_DEAD		0xDEADBEEF
387 #define MAC_REG_POOL_COUNT	10
388 #define ACCESS_CMAC(_addr) \
389 	({typeof(_addr) __addr = (_addr); \
390 	  __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
391 
392 #define PTCL_IDLE_POLL_CNT	10000
393 #define SW_CVR_DUR_US	8
394 #define SW_CVR_CNT	8
395 
396 #define DLE_BOUND_UNIT (8 * 1024)
397 #define DLE_WAIT_CNT 2000
398 #define TRXCFG_WAIT_CNT	2000
399 
400 #define RTW89_WDE_PG_64		64
401 #define RTW89_WDE_PG_128	128
402 #define RTW89_WDE_PG_256	256
403 
404 #define S_AX_WDE_PAGE_SEL_64	0
405 #define S_AX_WDE_PAGE_SEL_128	1
406 #define S_AX_WDE_PAGE_SEL_256	2
407 
408 #define RTW89_PLE_PG_64		64
409 #define RTW89_PLE_PG_128	128
410 #define RTW89_PLE_PG_256	256
411 
412 #define S_AX_PLE_PAGE_SEL_64	0
413 #define S_AX_PLE_PAGE_SEL_128	1
414 #define S_AX_PLE_PAGE_SEL_256	2
415 
416 #define SDIO_LOCAL_BASE_ADDR    0x80000000
417 
418 #define	PWR_CMD_WRITE		0
419 #define	PWR_CMD_POLL		1
420 #define	PWR_CMD_DELAY		2
421 #define	PWR_CMD_END		3
422 
423 #define	PWR_INTF_MSK_SDIO	BIT(0)
424 #define	PWR_INTF_MSK_USB	BIT(1)
425 #define	PWR_INTF_MSK_PCIE	BIT(2)
426 #define	PWR_INTF_MSK_ALL	0x7
427 
428 #define PWR_BASE_MAC		0
429 #define PWR_BASE_USB		1
430 #define PWR_BASE_PCIE		2
431 #define PWR_BASE_SDIO		3
432 
433 #define	PWR_CV_MSK_A		BIT(0)
434 #define	PWR_CV_MSK_B		BIT(1)
435 #define	PWR_CV_MSK_C		BIT(2)
436 #define	PWR_CV_MSK_D		BIT(3)
437 #define	PWR_CV_MSK_E		BIT(4)
438 #define	PWR_CV_MSK_F		BIT(5)
439 #define	PWR_CV_MSK_G		BIT(6)
440 #define	PWR_CV_MSK_TEST		BIT(7)
441 #define	PWR_CV_MSK_ALL		0xFF
442 
443 #define	PWR_DELAY_US		0
444 #define	PWR_DELAY_MS		1
445 
446 /* STA scheduler */
447 #define SS_MACID_SH		8
448 #define SS_TX_LEN_MSK		0x1FFFFF
449 #define SS_CTRL1_R_TX_LEN	5
450 #define SS_CTRL1_R_NEXT_LINK	20
451 #define SS_LINK_SIZE		256
452 
453 /* MAC debug port */
454 #define TMAC_DBG_SEL_C0 0xA5
455 #define RMAC_DBG_SEL_C0 0xA6
456 #define TRXPTCL_DBG_SEL_C0 0xA7
457 #define TMAC_DBG_SEL_C1 0xB5
458 #define RMAC_DBG_SEL_C1 0xB6
459 #define TRXPTCL_DBG_SEL_C1 0xB7
460 #define FW_PROG_CNTR_DBG_SEL 0xF2
461 #define PCIE_TXDMA_DBG_SEL 0x30
462 #define PCIE_RXDMA_DBG_SEL 0x31
463 #define PCIE_CVT_DBG_SEL 0x32
464 #define PCIE_CXPL_DBG_SEL 0x33
465 #define PCIE_IO_DBG_SEL 0x37
466 #define PCIE_MISC_DBG_SEL 0x38
467 #define PCIE_MISC2_DBG_SEL 0x00
468 #define MAC_DBG_SEL 1
469 #define RMAC_CMAC_DBG_SEL 1
470 
471 /* TRXPTCL dbg port sel */
472 #define TRXPTRL_DBG_SEL_TMAC 0
473 #define TRXPTRL_DBG_SEL_RMAC 1
474 
475 struct rtw89_cpuio_ctrl {
476 	u16 pkt_num;
477 	u16 start_pktid;
478 	u16 end_pktid;
479 	u8 cmd_type;
480 	u8 macid;
481 	u8 src_pid;
482 	u8 src_qid;
483 	u8 dst_pid;
484 	u8 dst_qid;
485 	u16 pktid;
486 };
487 
488 struct rtw89_mac_dbg_port_info {
489 	u32 sel_addr;
490 	u8 sel_byte;
491 	u32 sel_msk;
492 	u32 srt;
493 	u32 end;
494 	u32 rd_addr;
495 	u8 rd_byte;
496 	u32 rd_msk;
497 };
498 
499 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
500 #define QLNKTBL_ADDR_INFO_SEL_0 0
501 #define QLNKTBL_ADDR_INFO_SEL_1 1
502 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
503 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
504 
505 struct rtw89_mac_dle_dfi_ctrl {
506 	enum rtw89_mac_dle_ctrl_type type;
507 	u32 target;
508 	u32 addr;
509 	u32 out_data;
510 };
511 
512 struct rtw89_mac_dle_dfi_quota {
513 	enum rtw89_mac_dle_ctrl_type dle_type;
514 	u32 qtaid;
515 	u16 rsv_pgnum;
516 	u16 use_pgnum;
517 };
518 
519 struct rtw89_mac_dle_dfi_qempty {
520 	enum rtw89_mac_dle_ctrl_type dle_type;
521 	u32 grpsel;
522 	u32 qempty;
523 };
524 
525 enum rtw89_mac_error_scenario {
526 	RTW89_WCPU_CPU_EXCEPTION	= 2,
527 	RTW89_WCPU_ASSERTION		= 3,
528 };
529 
530 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
531 
532 /* Define DBG and recovery enum */
533 enum mac_ax_err_info {
534 	/* Get error info */
535 
536 	/* L0 */
537 	MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
538 	MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
539 	MAC_AX_ERR_L0_RESET_DONE = 0x0003,
540 	MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
541 
542 	/* L1 */
543 	MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
544 	MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
545 	MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
546 	MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
547 	MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
548 
549 	/* L2 */
550 	/* address hole (master) */
551 	MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
552 	MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
553 	MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
554 	MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
555 	MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
556 	MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
557 	MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
558 	MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
559 
560 	/* AHB bridge timeout (master) */
561 	MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
562 	MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
563 	MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
564 	MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
565 	MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
566 	MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
567 	MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
568 	MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
569 
570 	/* APB_SA bridge timeout (master + slave) */
571 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
572 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
573 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
574 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
575 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
576 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
577 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
578 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
579 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
580 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
581 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
582 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
583 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
584 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
585 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
586 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
587 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
588 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
589 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
590 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
591 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
592 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
593 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
594 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
595 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
596 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
597 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
598 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
599 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
600 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
601 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
602 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
603 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
604 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
605 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
606 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
607 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
608 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
609 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
610 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
611 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
612 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
613 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
614 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
615 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
616 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
617 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
618 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
619 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
620 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
621 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
622 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
623 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
624 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
625 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
626 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
627 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
628 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
629 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
630 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
631 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
632 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
633 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
634 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
635 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
636 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
637 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
638 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
639 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
640 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
641 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
642 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
643 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
644 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
645 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
646 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
647 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
648 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
649 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
650 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
651 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
652 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
653 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
654 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
655 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
656 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
657 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
658 
659 	/* APB_BBRF bridge timeout (master) */
660 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
661 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
662 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
663 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
664 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
665 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
666 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
667 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
668 	MAC_AX_ERR_L2_RESET_DONE = 0x2400,
669 	MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
670 	MAC_AX_ERR_ASSERTION = 0x4000,
671 	MAC_AX_GET_ERR_MAX,
672 	MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
673 
674 	/* set error info */
675 	MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
676 	MAC_AX_ERR_L1_RCVY_EN = 0x0002,
677 	MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
678 	MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
679 	MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
680 	MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
681 	MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
682 	MAC_AX_ERR_L0_RCVY_EN = 0x0013,
683 	MAC_AX_SET_ERR_MAX,
684 };
685 
686 struct rtw89_mac_size_set {
687 	const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
688 	const struct rtw89_dle_size wde_size0;
689 	const struct rtw89_dle_size wde_size4;
690 	const struct rtw89_dle_size wde_size18;
691 	const struct rtw89_dle_size wde_size19;
692 	const struct rtw89_dle_size ple_size0;
693 	const struct rtw89_dle_size ple_size4;
694 	const struct rtw89_dle_size ple_size18;
695 	const struct rtw89_dle_size ple_size19;
696 	const struct rtw89_wde_quota wde_qt0;
697 	const struct rtw89_wde_quota wde_qt4;
698 	const struct rtw89_wde_quota wde_qt17;
699 	const struct rtw89_wde_quota wde_qt18;
700 	const struct rtw89_ple_quota ple_qt4;
701 	const struct rtw89_ple_quota ple_qt5;
702 	const struct rtw89_ple_quota ple_qt13;
703 	const struct rtw89_ple_quota ple_qt44;
704 	const struct rtw89_ple_quota ple_qt45;
705 	const struct rtw89_ple_quota ple_qt46;
706 	const struct rtw89_ple_quota ple_qt47;
707 };
708 
709 extern const struct rtw89_mac_size_set rtw89_mac_size;
710 
rtw89_mac_reg_by_idx(u32 reg_base,u8 band)711 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band)
712 {
713 	return band == 0 ? reg_base : (reg_base + 0x2000);
714 }
715 
rtw89_mac_reg_by_port(u32 base,u8 port,u8 mac_idx)716 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx)
717 {
718 	return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx);
719 }
720 
721 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask)722 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
723 		       u32 base, u32 mask)
724 {
725 	u32 reg;
726 
727 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
728 	return rtw89_read32_mask(rtwdev, reg, mask);
729 }
730 
731 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 data)732 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
733 		   u32 data)
734 {
735 	u32 reg;
736 
737 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
738 	rtw89_write32(rtwdev, reg, data);
739 }
740 
741 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u32 data)742 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
743 			u32 base, u32 mask, u32 data)
744 {
745 	u32 reg;
746 
747 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
748 	rtw89_write32_mask(rtwdev, reg, mask, data);
749 }
750 
751 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u16 data)752 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
753 			u32 base, u32 mask, u16 data)
754 {
755 	u32 reg;
756 
757 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
758 	rtw89_write16_mask(rtwdev, reg, mask, data);
759 }
760 
761 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)762 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
763 		       u32 base, u32 bit)
764 {
765 	u32 reg;
766 
767 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
768 	rtw89_write32_clr(rtwdev, reg, bit);
769 }
770 
771 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u16 bit)772 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
773 		       u32 base, u16 bit)
774 {
775 	u32 reg;
776 
777 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
778 	rtw89_write16_clr(rtwdev, reg, bit);
779 }
780 
781 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)782 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
783 		       u32 base, u32 bit)
784 {
785 	u32 reg;
786 
787 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
788 	rtw89_write32_set(rtwdev, reg, bit);
789 }
790 
791 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
792 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev);
793 int rtw89_mac_init(struct rtw89_dev *rtwdev);
794 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
795 			   enum rtw89_mac_hwmod_sel sel);
796 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
797 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
798 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
799 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
800 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
801 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
802 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
803 
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)804 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
805 {
806 	const struct rtw89_chip_info *chip = rtwdev->chip;
807 
808 	return chip->ops->enable_bb_rf(rtwdev);
809 }
810 
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)811 static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
812 {
813 	const struct rtw89_chip_info *chip = rtwdev->chip;
814 
815 	chip->ops->disable_bb_rf(rtwdev);
816 }
817 
818 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
819 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
820 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
821 			  u32 len, u8 class, u8 func);
822 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
823 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
824 			  u32 *tx_en, enum rtw89_sch_tx_sel sel);
825 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
826 			     u32 *tx_en, enum rtw89_sch_tx_sel sel);
827 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
828 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
829 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable);
830 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
831 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
832 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
833 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
834 			   const struct rtw89_mac_ax_coex *coex);
835 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
836 		      const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
837 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
838 			 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
839 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
840 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band);
841 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
842 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
843 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
844 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
845 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
846 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
847 			    enum rtw89_phy_idx phy_idx,
848 			    u32 reg_base, u32 *cr);
849 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
850 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
851 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
852 			struct ieee80211_sta *sta);
853 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
854 			   struct ieee80211_sta *sta);
855 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
856 				struct ieee80211_bss_conf *conf);
857 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
858 			       struct ieee80211_sta *sta, bool disconnect);
859 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
860 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
861 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
862 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
863 				 struct rtw89_vif *rtwvif, bool en);
864 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
865 
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)866 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
867 {
868 	if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
869 		return;
870 
871 	_rtw89_mac_bf_monitor_track(rtwdev);
872 }
873 
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)874 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
875 					 enum rtw89_phy_idx phy_idx,
876 					 u32 reg_base, u32 *val)
877 {
878 	u32 cr;
879 
880 	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
881 		return -EINVAL;
882 
883 	*val = rtw89_read32(rtwdev, cr);
884 	return 0;
885 }
886 
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)887 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
888 					  enum rtw89_phy_idx phy_idx,
889 					  u32 reg_base, u32 val)
890 {
891 	u32 cr;
892 
893 	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
894 		return -EINVAL;
895 
896 	rtw89_write32(rtwdev, cr, val);
897 	return 0;
898 }
899 
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)900 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
901 					       enum rtw89_phy_idx phy_idx,
902 					       u32 reg_base, u32 mask, u32 val)
903 {
904 	u32 cr;
905 
906 	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
907 		return -EINVAL;
908 
909 	rtw89_write32_mask(rtwdev, cr, mask, val);
910 	return 0;
911 }
912 
913 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
914 			  bool resume, u32 tx_time);
915 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
916 			  u32 *tx_time);
917 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
918 				 struct rtw89_sta *rtwsta,
919 				 bool resume, u8 tx_retry);
920 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
921 				 struct rtw89_sta *rtwsta, u8 *tx_retry);
922 
923 enum rtw89_mac_xtal_si_offset {
924 	XTAL0 = 0x0,
925 	XTAL3 = 0x3,
926 	XTAL_SI_XTAL_SC_XI = 0x04,
927 #define XTAL_SC_XI_MASK		GENMASK(7, 0)
928 	XTAL_SI_XTAL_SC_XO = 0x05,
929 #define XTAL_SC_XO_MASK		GENMASK(7, 0)
930 	XTAL_SI_PWR_CUT = 0x10,
931 #define XTAL_SI_SMALL_PWR_CUT	BIT(0)
932 #define XTAL_SI_BIG_PWR_CUT	BIT(1)
933 	XTAL_SI_XTAL_XMD_2 = 0x24,
934 #define XTAL_SI_LDO_LPS		GENMASK(6, 4)
935 	XTAL_SI_XTAL_XMD_4 = 0x26,
936 #define XTAL_SI_LPS_CAP		GENMASK(3, 0)
937 	XTAL_SI_CV = 0x41,
938 	XTAL_SI_LOW_ADDR = 0x62,
939 #define XTAL_SI_LOW_ADDR_MASK	GENMASK(7, 0)
940 	XTAL_SI_CTRL = 0x63,
941 #define XTAL_SI_MODE_SEL_MASK	GENMASK(7, 6)
942 #define XTAL_SI_RDY		BIT(5)
943 #define XTAL_SI_HIGH_ADDR_MASK	GENMASK(2, 0)
944 	XTAL_SI_READ_VAL = 0x7A,
945 	XTAL_SI_WL_RFC_S0 = 0x80,
946 #define XTAL_SI_RF00		BIT(0)
947 	XTAL_SI_WL_RFC_S1 = 0x81,
948 #define XTAL_SI_RF10		BIT(0)
949 	XTAL_SI_ANAPAR_WL = 0x90,
950 #define XTAL_SI_SRAM2RFC	BIT(7)
951 #define XTAL_SI_GND_SHDN_WL	BIT(6)
952 #define XTAL_SI_SHDN_WL		BIT(5)
953 #define XTAL_SI_RFC2RF		BIT(4)
954 #define XTAL_SI_OFF_EI		BIT(3)
955 #define XTAL_SI_OFF_WEI		BIT(2)
956 #define XTAL_SI_PON_EI		BIT(1)
957 #define XTAL_SI_PON_WEI		BIT(0)
958 	XTAL_SI_SRAM_CTRL = 0xA1,
959 #define FULL_BIT_MASK		GENMASK(7, 0)
960 };
961 
962 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
963 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
964 
965 #endif
966