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Searched refs:REG_SET_3 (Results 1 – 22 of 22) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_ipp.c104 REG_SET_3(CUR_COLOR1, 0, in dce_ipp_cursor_set_attributes()
109 REG_SET_3(CUR_COLOR2, 0, in dce_ipp_cursor_set_attributes()
189 REG_SET_3(DC_LUT_CONTROL, 0, in dce_ipp_program_input_lut()
228 REG_SET_3(DEGAMMA_CONTROL, 0, in dce_ipp_set_degamma()
Ddce_abm.c148 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dce_abm_init()
153 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dce_abm_init()
171 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dce_abm_init()
Ddmub_abm.c89 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dmub_abm_init()
94 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dmub_abm_init()
112 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dmub_abm_init()
Ddce_i2c_hw.c110 REG_SET_3(DC_I2C_DATA, 0, in process_channel_reply()
Ddce_link_encoder.c176 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
184 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
Ddce_transform.c237 REG_SET_3(SCL_COEF_RAM_SELECT, 0, in program_multi_taps_filter()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_optc.c91 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc3_lock_doublebuffer_enable()
138 REG_SET_3(OTG_BLANK_DATA_COLOR, 0, in optc3_program_blank_color()
143 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0, in optc3_program_blank_color()
258 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc3_set_odm_combine()
Ddcn30_mmhubbub.c89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub3_warmup_mcif()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_opp.c223 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
234 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
245 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
Ddcn20_optc.c167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_bypass()
210 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_combine()
433 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc2_lock_doublebuffer_enable()
Ddcn20_dsc.c596 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
630 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
647 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
Ddcn20_hubp.c151 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp2_program_deadline()
156 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp2_program_deadline()
161 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp2_program_deadline()
667 REG_SET_3(DMDATA_QOS_CNTL, 0, in hubp2_dmdata_set_attributes()
Ddcn20_dwb_scl.c701 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0, in wbscl_set_scaler_filter()
/linux-5.19.10/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp.c304 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
310 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
Ddcn10_dpp_dscl.c255 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp1_dscl_set_scaler_filter()
653 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_manual_scale()
Ddcn10_optc.c547 REG_SET_3(OTG_BLACK_COLOR, 0, in optc1_program_blank_color()
741 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
750 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
Ddcn10_hubp.c658 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp1_program_deadline()
663 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp1_program_deadline()
668 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp1_program_deadline()
Ddcn10_link_encoder.c147 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
155 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
Ddcn10_dpp_cm.c714 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_optc.c74 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc31_set_odm_combine()
/linux-5.19.10/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro