1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Apple SoC pinctrl+GPIO+external IRQ driver
4  *
5  * Copyright (C) The Asahi Linux Contributors
6  * Copyright (C) 2020 Corellium LLC
7  *
8  * Based on: pinctrl-pistachio.c
9  * Copyright (C) 2014 Imagination Technologies Ltd.
10  * Copyright (C) 2014 Google, Inc.
11  */
12 
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <linux/bits.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_irq.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 
26 #include "pinctrl-utils.h"
27 #include "core.h"
28 #include "pinmux.h"
29 
30 struct apple_gpio_pinctrl {
31 	struct device *dev;
32 	struct pinctrl_dev *pctldev;
33 
34 	void __iomem *base;
35 	struct regmap *map;
36 
37 	struct pinctrl_desc pinctrl_desc;
38 	struct gpio_chip gpio_chip;
39 	u8 irqgrps[];
40 };
41 
42 #define REG_GPIO(x)          (4 * (x))
43 #define REG_GPIOx_DATA       BIT(0)
44 #define REG_GPIOx_MODE       GENMASK(3, 1)
45 #define REG_GPIOx_OUT        1
46 #define REG_GPIOx_IN_IRQ_HI  2
47 #define REG_GPIOx_IN_IRQ_LO  3
48 #define REG_GPIOx_IN_IRQ_UP  4
49 #define REG_GPIOx_IN_IRQ_DN  5
50 #define REG_GPIOx_IN_IRQ_ANY 6
51 #define REG_GPIOx_IN_IRQ_OFF 7
52 #define REG_GPIOx_PERIPH     GENMASK(6, 5)
53 #define REG_GPIOx_PULL       GENMASK(8, 7)
54 #define REG_GPIOx_PULL_OFF   0
55 #define REG_GPIOx_PULL_DOWN  1
56 #define REG_GPIOx_PULL_UP_STRONG 2
57 #define REG_GPIOx_PULL_UP    3
58 #define REG_GPIOx_INPUT_ENABLE BIT(9)
59 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
60 #define REG_GPIOx_SCHMITT    BIT(15)
61 #define REG_GPIOx_GRP        GENMASK(18, 16)
62 #define REG_GPIOx_LOCK       BIT(21)
63 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
64 #define REG_IRQ(g, x)        (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
65 
66 struct regmap_config regmap_config = {
67 	.reg_bits = 32,
68 	.val_bits = 32,
69 	.reg_stride = 4,
70 	.cache_type = REGCACHE_FLAT,
71 	.max_register = 512 * sizeof(u32),
72 	.num_reg_defaults_raw = 512,
73 	.use_relaxed_mmio = true,
74 	.use_raw_spinlock = true,
75 };
76 
77 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
apple_gpio_set_reg(struct apple_gpio_pinctrl * pctl,unsigned int pin,u32 mask,u32 value)78 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
79                                unsigned int pin, u32 mask, u32 value)
80 {
81 	regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
82 }
83 
apple_gpio_get_reg(struct apple_gpio_pinctrl * pctl,unsigned int pin)84 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
85                               unsigned int pin)
86 {
87 	int ret;
88 	u32 val;
89 
90 	ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
91 	if (ret)
92 		return 0;
93 
94 	return val;
95 }
96 
97 /* Pin controller functions */
98 
apple_gpio_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * node,struct pinctrl_map ** map,unsigned * num_maps)99 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
100                                      struct device_node *node,
101                                      struct pinctrl_map **map,
102                                      unsigned *num_maps)
103 {
104 	unsigned reserved_maps;
105 	struct apple_gpio_pinctrl *pctl;
106 	u32 pinfunc, pin, func;
107 	int num_pins, i, ret;
108 	const char *group_name;
109 	const char *function_name;
110 
111 	*map = NULL;
112 	*num_maps = 0;
113 	reserved_maps = 0;
114 
115 	pctl = pinctrl_dev_get_drvdata(pctldev);
116 
117 	ret = of_property_count_u32_elems(node, "pinmux");
118 	if (ret <= 0) {
119 		dev_err(pctl->dev,
120 			"missing or empty pinmux property in node %pOFn.\n",
121 			node);
122 		return ret ? ret : -EINVAL;
123 	}
124 
125 	num_pins = ret;
126 
127 	ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
128 	if (ret)
129 		return ret;
130 
131 	for (i = 0; i < num_pins; i++) {
132 		ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
133 		if (ret)
134 			goto free_map;
135 
136 		pin = APPLE_PIN(pinfunc);
137 		func = APPLE_FUNC(pinfunc);
138 
139 		if (func >= pinmux_generic_get_function_count(pctldev)) {
140 			ret = -EINVAL;
141 			goto free_map;
142 		}
143 
144 		group_name = pinctrl_generic_get_group_name(pctldev, pin);
145 		function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
146 		ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
147 		                                &reserved_maps, num_maps,
148 		                                group_name, function_name);
149 		if (ret)
150 			goto free_map;
151 	}
152 
153 free_map:
154 	if (ret < 0)
155 		pinctrl_utils_free_map(pctldev, *map, *num_maps);
156 
157 	return ret;
158 }
159 
160 static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
161 	.get_groups_count = pinctrl_generic_get_group_count,
162 	.get_group_name = pinctrl_generic_get_group_name,
163 	.get_group_pins = pinctrl_generic_get_group_pins,
164 	.dt_node_to_map = apple_gpio_dt_node_to_map,
165 	.dt_free_map = pinctrl_utils_free_map,
166 };
167 
168 /* Pin multiplexer functions */
169 
apple_gpio_pinmux_set(struct pinctrl_dev * pctldev,unsigned func,unsigned group)170 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
171                                  unsigned group)
172 {
173 	struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
174 
175 	apple_gpio_set_reg(
176 		pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
177 		FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);
178 
179 	return 0;
180 }
181 
182 static const struct pinmux_ops apple_gpio_pinmux_ops = {
183 	.get_functions_count = pinmux_generic_get_function_count,
184 	.get_function_name = pinmux_generic_get_function_name,
185 	.get_function_groups = pinmux_generic_get_function_groups,
186 	.set_mux = apple_gpio_pinmux_set,
187 	.strict = true,
188 };
189 
190 /* GPIO chip functions */
191 
apple_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)192 static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
193 {
194 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
195 	unsigned int reg = apple_gpio_get_reg(pctl, offset);
196 
197 	if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
198 		return GPIO_LINE_DIRECTION_OUT;
199 	return GPIO_LINE_DIRECTION_IN;
200 }
201 
apple_gpio_get(struct gpio_chip * chip,unsigned offset)202 static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
203 {
204 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
205 	unsigned int reg = apple_gpio_get_reg(pctl, offset);
206 
207 	/*
208 	 * If this is an input GPIO, read the actual value (not the
209 	 * cached regmap value)
210 	 */
211 	if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
212 		reg = readl_relaxed(pctl->base + REG_GPIO(offset));
213 
214 	return !!(reg & REG_GPIOx_DATA);
215 }
216 
apple_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)217 static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
218 {
219 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
220 
221 	apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
222 }
223 
apple_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)224 static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
225 {
226 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
227 
228 	apple_gpio_set_reg(pctl, offset,
229 			   REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
230 				   REG_GPIOx_INPUT_ENABLE,
231 			   FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
232 				   REG_GPIOx_INPUT_ENABLE);
233 	return 0;
234 }
235 
apple_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)236 static int apple_gpio_direction_output(struct gpio_chip *chip,
237                                        unsigned int offset, int value)
238 {
239 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
240 
241 	apple_gpio_set_reg(pctl, offset,
242 			   REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
243 			   FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
244 				   (value ? REG_GPIOx_DATA : 0));
245 	return 0;
246 }
247 
248 /* IRQ chip functions */
249 
apple_gpio_irq_ack(struct irq_data * data)250 static void apple_gpio_irq_ack(struct irq_data *data)
251 {
252 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
253 	unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
254 
255 	writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
256 }
257 
apple_gpio_irq_type(unsigned int type)258 static unsigned int apple_gpio_irq_type(unsigned int type)
259 {
260 	switch (type & IRQ_TYPE_SENSE_MASK) {
261 	case IRQ_TYPE_EDGE_RISING:
262 		return REG_GPIOx_IN_IRQ_UP;
263 	case IRQ_TYPE_EDGE_FALLING:
264 		return REG_GPIOx_IN_IRQ_DN;
265 	case IRQ_TYPE_EDGE_BOTH:
266 		return REG_GPIOx_IN_IRQ_ANY;
267 	case IRQ_TYPE_LEVEL_HIGH:
268 		return REG_GPIOx_IN_IRQ_HI;
269 	case IRQ_TYPE_LEVEL_LOW:
270 		return REG_GPIOx_IN_IRQ_LO;
271 	default:
272 		return REG_GPIOx_IN_IRQ_OFF;
273 	}
274 }
275 
apple_gpio_irq_mask(struct irq_data * data)276 static void apple_gpio_irq_mask(struct irq_data *data)
277 {
278 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
279 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
280 
281 	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
282 	                   FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
283 	gpiochip_disable_irq(gc, data->hwirq);
284 }
285 
apple_gpio_irq_unmask(struct irq_data * data)286 static void apple_gpio_irq_unmask(struct irq_data *data)
287 {
288 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
289 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
290 	unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
291 
292 	gpiochip_enable_irq(gc, data->hwirq);
293 	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
294 	                   FIELD_PREP(REG_GPIOx_MODE, irqtype));
295 }
296 
apple_gpio_irq_startup(struct irq_data * data)297 static unsigned int apple_gpio_irq_startup(struct irq_data *data)
298 {
299 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
300 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
301 
302 	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
303 	                   FIELD_PREP(REG_GPIOx_GRP, 0));
304 
305 	apple_gpio_direction_input(chip, data->hwirq);
306 	apple_gpio_irq_unmask(data);
307 
308 	return 0;
309 }
310 
apple_gpio_irq_set_type(struct irq_data * data,unsigned int type)311 static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
312 {
313 	struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
314 	unsigned int irqtype = apple_gpio_irq_type(type);
315 
316 	if (irqtype == REG_GPIOx_IN_IRQ_OFF)
317 		return -EINVAL;
318 
319 	apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
320 	                   FIELD_PREP(REG_GPIOx_MODE, irqtype));
321 
322 	if (type & IRQ_TYPE_LEVEL_MASK)
323 		irq_set_handler_locked(data, handle_level_irq);
324 	else
325 		irq_set_handler_locked(data, handle_edge_irq);
326 	return 0;
327 }
328 
apple_gpio_irq_handler(struct irq_desc * desc)329 static void apple_gpio_irq_handler(struct irq_desc *desc)
330 {
331 	struct irq_chip *chip = irq_desc_get_chip(desc);
332 	u8 *grpp = irq_desc_get_handler_data(desc);
333 	struct apple_gpio_pinctrl *pctl;
334 	unsigned int pinh, pinl;
335 	unsigned long pending;
336 	struct gpio_chip *gc;
337 
338 	pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
339 	gc = &pctl->gpio_chip;
340 
341 	chained_irq_enter(chip, desc);
342 	for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
343 		pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
344 		for_each_set_bit(pinl, &pending, 32)
345 			generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
346 	}
347 	chained_irq_exit(chip, desc);
348 }
349 
350 static const struct irq_chip apple_gpio_irqchip = {
351 	.name			= "Apple-GPIO",
352 	.irq_startup		= apple_gpio_irq_startup,
353 	.irq_ack		= apple_gpio_irq_ack,
354 	.irq_mask		= apple_gpio_irq_mask,
355 	.irq_unmask		= apple_gpio_irq_unmask,
356 	.irq_set_type		= apple_gpio_irq_set_type,
357 	.flags			= IRQCHIP_IMMUTABLE,
358 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
359 };
360 
361 /* Probe & register */
362 
apple_gpio_register(struct apple_gpio_pinctrl * pctl)363 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
364 {
365 	struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
366 	void **irq_data = NULL;
367 	int ret;
368 
369 	pctl->gpio_chip.label = dev_name(pctl->dev);
370 	pctl->gpio_chip.request = gpiochip_generic_request;
371 	pctl->gpio_chip.free = gpiochip_generic_free;
372 	pctl->gpio_chip.get_direction = apple_gpio_get_direction;
373 	pctl->gpio_chip.direction_input = apple_gpio_direction_input;
374 	pctl->gpio_chip.direction_output = apple_gpio_direction_output;
375 	pctl->gpio_chip.get = apple_gpio_get;
376 	pctl->gpio_chip.set = apple_gpio_set;
377 	pctl->gpio_chip.base = -1;
378 	pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
379 	pctl->gpio_chip.parent = pctl->dev;
380 
381 	if (girq->num_parents) {
382 		int i;
383 
384 		gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip);
385 		girq->parent_handler = apple_gpio_irq_handler;
386 
387 		girq->parents = kmalloc_array(girq->num_parents,
388 					      sizeof(*girq->parents),
389 					      GFP_KERNEL);
390 		irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
391 					 GFP_KERNEL);
392 		if (!girq->parents || !irq_data) {
393 			ret = -ENOMEM;
394 			goto out_free_irq_data;
395 		}
396 
397 		for (i = 0; i < girq->num_parents; i++) {
398 			ret = platform_get_irq(to_platform_device(pctl->dev), i);
399 			if (ret < 0)
400 				goto out_free_irq_data;
401 
402 			girq->parents[i] = ret;
403 			pctl->irqgrps[i] = i;
404 			irq_data[i] = &pctl->irqgrps[i];
405 		}
406 
407 		girq->parent_handler_data_array = irq_data;
408 		girq->per_parent_data = true;
409 		girq->default_type = IRQ_TYPE_NONE;
410 		girq->handler = handle_level_irq;
411 	}
412 
413 	ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
414 
415 out_free_irq_data:
416 	kfree(girq->parents);
417 	kfree(irq_data);
418 
419 	return ret;
420 }
421 
apple_gpio_pinctrl_probe(struct platform_device * pdev)422 static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
423 {
424 	struct apple_gpio_pinctrl *pctl;
425 	struct pinctrl_pin_desc *pins;
426 	unsigned int npins;
427 	const char **pin_names;
428 	unsigned int *pin_nums;
429 	static const char* pinmux_functions[] = {
430 		"gpio", "periph1", "periph2", "periph3"
431 	};
432 	unsigned int i, nirqs = 0;
433 	int res;
434 
435 	if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
436 		res = platform_irq_count(pdev);
437 		if (res > 0)
438 			nirqs = res;
439 	}
440 
441 	pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
442 			    GFP_KERNEL);
443 	if (!pctl)
444 		return -ENOMEM;
445 	pctl->dev = &pdev->dev;
446 	pctl->gpio_chip.irq.num_parents = nirqs;
447 	dev_set_drvdata(&pdev->dev, pctl);
448 
449 	if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
450 		return dev_err_probe(&pdev->dev, -EINVAL,
451 				     "apple,npins property not found\n");
452 
453 	pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
454 				  GFP_KERNEL);
455 	pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
456 				       GFP_KERNEL);
457 	pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
458 				      GFP_KERNEL);
459 	if (!pins || !pin_names || !pin_nums)
460 		return -ENOMEM;
461 
462 	pctl->base = devm_platform_ioremap_resource(pdev, 0);
463 	if (IS_ERR(pctl->base))
464 		return PTR_ERR(pctl->base);
465 
466 	pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, &regmap_config);
467 	if (IS_ERR(pctl->map))
468 		return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
469 				     "Failed to create regmap\n");
470 
471 	for (i = 0; i < npins; i++) {
472 		pins[i].number = i;
473 		pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
474 		pins[i].drv_data = pctl;
475 		pin_names[i] = pins[i].name;
476 		pin_nums[i] = i;
477 	}
478 
479 	pctl->pinctrl_desc.name = dev_name(pctl->dev);
480 	pctl->pinctrl_desc.pins = pins;
481 	pctl->pinctrl_desc.npins = npins;
482 	pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
483 	pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
484 
485 	pctl->pctldev =	devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
486 	if (IS_ERR(pctl->pctldev))
487 		return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
488 				     "Failed to register pinctrl device.\n");
489 
490 	for (i = 0; i < npins; i++) {
491 		res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
492 						pin_nums + i, 1, pctl);
493 		if (res < 0)
494 			return dev_err_probe(pctl->dev, res,
495 					     "Failed to register group");
496 	}
497 
498 	for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
499 		res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
500 						  pin_names, npins, pctl);
501 		if (res < 0)
502 			return dev_err_probe(pctl->dev, res,
503 					     "Failed to register function.");
504 	}
505 
506 	return apple_gpio_register(pctl);
507 }
508 
509 static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
510 	{ .compatible = "apple,pinctrl", },
511 	{ }
512 };
513 MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);
514 
515 static struct platform_driver apple_gpio_pinctrl_driver = {
516 	.driver = {
517 		.name = "apple-gpio-pinctrl",
518 		.of_match_table = apple_gpio_pinctrl_of_match,
519 		.suppress_bind_attrs = true,
520 	},
521 	.probe = apple_gpio_pinctrl_probe,
522 };
523 module_platform_driver(apple_gpio_pinctrl_driver);
524 
525 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
526 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
527 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
528 MODULE_LICENSE("GPL v2");
529