Searched refs:REG_DSI_7nm_PHY_CMN_CLK_CFG1 (Results 1 – 2 of 2) sorted by relevance
332 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()333 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); in dsi_pll_disable_global_clk()342 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()343 dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, in dsi_pll_enable_global_clk()510 cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_7nm_pll_save_state()534 val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_7nm_pll_restore_state()537 dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); in dsi_7nm_pll_restore_state()575 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); in dsi_7nm_set_usecase()682 data = dsi_phy_read(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in pll_7nm_register()683 dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data | 3); in pll_7nm_register()[all …]
66 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014 macro