Searched refs:REG_A4XX_CP_RB_WPTR (Results 1 – 2 of 2) sorted by relevance
69 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit()179 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_me_init()
2135 #define REG_A4XX_CP_RB_WPTR 0x00000205 macro