1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef ATH11K_QMI_H
8 #define ATH11K_QMI_H
9 
10 #include <linux/mutex.h>
11 #include <linux/soc/qcom/qmi.h>
12 
13 #define ATH11K_HOST_VERSION_STRING		"WIN"
14 #define ATH11K_QMI_WLANFW_TIMEOUT_MS		10000
15 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE	64
16 #define ATH11K_QMI_CALDB_ADDRESS		0x4BA00000
17 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01	128
18 #define ATH11K_QMI_WLFW_SERVICE_ID_V01		0x45
19 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01	0x01
20 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01	0x02
21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390	0x01
22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074	0x02
23 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074	0x07
24 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750	0x03
25 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01	32
26 #define ATH11K_QMI_RESP_LEN_MAX			8192
27 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01	52
28 #define ATH11K_QMI_CALDB_SIZE			0x480000
29 #define ATH11K_QMI_BDF_EXT_STR_LENGTH		0x20
30 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT	3
31 
32 #define QMI_WLFW_REQUEST_MEM_IND_V01		0x0035
33 #define QMI_WLFW_FW_MEM_READY_IND_V01		0x0037
34 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01	0x0021
35 #define QMI_WLFW_FW_READY_IND_V01		0x0038
36 
37 #define QMI_WLANFW_MAX_DATA_SIZE_V01		6144
38 #define ATH11K_FIRMWARE_MODE_OFF		4
39 #define ATH11K_COLD_BOOT_FW_RESET_DELAY		(40 * HZ)
40 
41 #define ATH11K_QMI_DEVICE_BAR_SIZE		0x200000
42 
43 struct ath11k_base;
44 
45 enum ath11k_qmi_file_type {
46 	ATH11K_QMI_FILE_TYPE_BDF_GOLDEN,
47 	ATH11K_QMI_FILE_TYPE_CALDATA = 2,
48 	ATH11K_QMI_FILE_TYPE_EEPROM,
49 	ATH11K_QMI_MAX_FILE_TYPE,
50 };
51 
52 enum ath11k_qmi_bdf_type {
53 	ATH11K_QMI_BDF_TYPE_BIN			= 0,
54 	ATH11K_QMI_BDF_TYPE_ELF			= 1,
55 	ATH11K_QMI_BDF_TYPE_REGDB		= 4,
56 };
57 
58 enum ath11k_qmi_event_type {
59 	ATH11K_QMI_EVENT_SERVER_ARRIVE,
60 	ATH11K_QMI_EVENT_SERVER_EXIT,
61 	ATH11K_QMI_EVENT_REQUEST_MEM,
62 	ATH11K_QMI_EVENT_FW_MEM_READY,
63 	ATH11K_QMI_EVENT_FW_READY,
64 	ATH11K_QMI_EVENT_COLD_BOOT_CAL_START,
65 	ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE,
66 	ATH11K_QMI_EVENT_REGISTER_DRIVER,
67 	ATH11K_QMI_EVENT_UNREGISTER_DRIVER,
68 	ATH11K_QMI_EVENT_RECOVERY,
69 	ATH11K_QMI_EVENT_FORCE_FW_ASSERT,
70 	ATH11K_QMI_EVENT_POWER_UP,
71 	ATH11K_QMI_EVENT_POWER_DOWN,
72 	ATH11K_QMI_EVENT_MAX,
73 };
74 
75 struct ath11k_qmi_driver_event {
76 	struct list_head list;
77 	enum ath11k_qmi_event_type type;
78 	void *data;
79 };
80 
81 struct ath11k_qmi_ce_cfg {
82 	const struct ce_pipe_config *tgt_ce;
83 	int tgt_ce_len;
84 	const struct service_to_pipe *svc_to_ce_map;
85 	int svc_to_ce_map_len;
86 	const u8 *shadow_reg;
87 	int shadow_reg_len;
88 	u32 *shadow_reg_v2;
89 	int shadow_reg_v2_len;
90 };
91 
92 struct ath11k_qmi_event_msg {
93 	struct list_head list;
94 	enum ath11k_qmi_event_type type;
95 };
96 
97 struct target_mem_chunk {
98 	u32 size;
99 	u32 type;
100 	u32 prev_size;
101 	u32 prev_type;
102 	dma_addr_t paddr;
103 	u32 *vaddr;
104 	void __iomem *iaddr;
105 };
106 
107 struct target_info {
108 	u32 chip_id;
109 	u32 chip_family;
110 	u32 board_id;
111 	u32 soc_id;
112 	u32 fw_version;
113 	u32 eeprom_caldata;
114 	char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
115 	char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
116 	char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH];
117 };
118 
119 struct m3_mem_region {
120 	u32 size;
121 	dma_addr_t paddr;
122 	void *vaddr;
123 };
124 
125 struct ath11k_qmi {
126 	struct ath11k_base *ab;
127 	struct qmi_handle handle;
128 	struct sockaddr_qrtr sq;
129 	struct work_struct event_work;
130 	struct workqueue_struct *event_wq;
131 	struct list_head event_list;
132 	spinlock_t event_lock; /* spinlock for qmi event list */
133 	struct ath11k_qmi_ce_cfg ce_cfg;
134 	struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
135 	u32 mem_seg_count;
136 	u32 target_mem_mode;
137 	bool target_mem_delayed;
138 	u8 cal_done;
139 	struct target_info target;
140 	struct m3_mem_region m3_mem;
141 	unsigned int service_ins_id;
142 	wait_queue_head_t cold_boot_waitq;
143 };
144 
145 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN		261
146 #define QMI_WLANFW_HOST_CAP_REQ_V01			0x0034
147 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN	7
148 #define QMI_WLFW_HOST_CAP_RESP_V01			0x0034
149 #define QMI_WLFW_MAX_NUM_GPIO_V01			32
150 #define QMI_IPQ8074_FW_MEM_MODE				0xFF
151 #define HOST_DDR_REGION_TYPE				0x1
152 #define BDF_MEM_REGION_TYPE				0x2
153 #define M3_DUMP_REGION_TYPE				0x3
154 #define CALDB_MEM_REGION_TYPE				0x4
155 
156 struct qmi_wlanfw_host_cap_req_msg_v01 {
157 	u8 num_clients_valid;
158 	u32 num_clients;
159 	u8 wake_msi_valid;
160 	u32 wake_msi;
161 	u8 gpios_valid;
162 	u32 gpios_len;
163 	u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
164 	u8 nm_modem_valid;
165 	u8 nm_modem;
166 	u8 bdf_support_valid;
167 	u8 bdf_support;
168 	u8 bdf_cache_support_valid;
169 	u8 bdf_cache_support;
170 	u8 m3_support_valid;
171 	u8 m3_support;
172 	u8 m3_cache_support_valid;
173 	u8 m3_cache_support;
174 	u8 cal_filesys_support_valid;
175 	u8 cal_filesys_support;
176 	u8 cal_cache_support_valid;
177 	u8 cal_cache_support;
178 	u8 cal_done_valid;
179 	u8 cal_done;
180 	u8 mem_bucket_valid;
181 	u32 mem_bucket;
182 	u8 mem_cfg_mode_valid;
183 	u8 mem_cfg_mode;
184 };
185 
186 struct qmi_wlanfw_host_cap_resp_msg_v01 {
187 	struct qmi_response_type_v01 resp;
188 };
189 
190 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN		54
191 #define QMI_WLANFW_IND_REGISTER_REQ_V01				0x0020
192 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN		18
193 #define QMI_WLANFW_IND_REGISTER_RESP_V01			0x0020
194 #define QMI_WLANFW_CLIENT_ID					0x4b4e454c
195 
196 struct qmi_wlanfw_ind_register_req_msg_v01 {
197 	u8 fw_ready_enable_valid;
198 	u8 fw_ready_enable;
199 	u8 initiate_cal_download_enable_valid;
200 	u8 initiate_cal_download_enable;
201 	u8 initiate_cal_update_enable_valid;
202 	u8 initiate_cal_update_enable;
203 	u8 msa_ready_enable_valid;
204 	u8 msa_ready_enable;
205 	u8 pin_connect_result_enable_valid;
206 	u8 pin_connect_result_enable;
207 	u8 client_id_valid;
208 	u32 client_id;
209 	u8 request_mem_enable_valid;
210 	u8 request_mem_enable;
211 	u8 fw_mem_ready_enable_valid;
212 	u8 fw_mem_ready_enable;
213 	u8 fw_init_done_enable_valid;
214 	u8 fw_init_done_enable;
215 	u8 rejuvenate_enable_valid;
216 	u32 rejuvenate_enable;
217 	u8 xo_cal_enable_valid;
218 	u8 xo_cal_enable;
219 	u8 cal_done_enable_valid;
220 	u8 cal_done_enable;
221 };
222 
223 struct qmi_wlanfw_ind_register_resp_msg_v01 {
224 	struct qmi_response_type_v01 resp;
225 	u8 fw_status_valid;
226 	u64 fw_status;
227 };
228 
229 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN	1824
230 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN	888
231 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN	7
232 #define QMI_WLANFW_REQUEST_MEM_IND_V01			0x0035
233 #define QMI_WLANFW_RESPOND_MEM_REQ_V01			0x0036
234 #define QMI_WLANFW_RESPOND_MEM_RESP_V01			0x0036
235 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01			2
236 
237 struct qmi_wlanfw_mem_cfg_s_v01 {
238 	u64 offset;
239 	u32 size;
240 	u8 secure_flag;
241 };
242 
243 enum qmi_wlanfw_mem_type_enum_v01 {
244 	WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
245 	QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
246 	QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
247 	QMI_WLANFW_MEM_BDF_V01 = 2,
248 	QMI_WLANFW_MEM_M3_V01 = 3,
249 	QMI_WLANFW_MEM_CAL_V01 = 4,
250 	QMI_WLANFW_MEM_DPD_V01 = 5,
251 	WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
252 };
253 
254 struct qmi_wlanfw_mem_seg_s_v01 {
255 	u32 size;
256 	enum qmi_wlanfw_mem_type_enum_v01 type;
257 	u32 mem_cfg_len;
258 	struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
259 };
260 
261 struct qmi_wlanfw_request_mem_ind_msg_v01 {
262 	u32 mem_seg_len;
263 	struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
264 };
265 
266 struct qmi_wlanfw_mem_seg_resp_s_v01 {
267 	u64 addr;
268 	u32 size;
269 	enum qmi_wlanfw_mem_type_enum_v01 type;
270 	u8 restore;
271 };
272 
273 struct qmi_wlanfw_respond_mem_req_msg_v01 {
274 	u32 mem_seg_len;
275 	struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
276 };
277 
278 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
279 	struct qmi_response_type_v01 resp;
280 };
281 
282 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
283 	char placeholder;
284 };
285 
286 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
287 	char placeholder;
288 };
289 
290 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 {
291 	char placeholder;
292 };
293 
294 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN		0
295 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN		235
296 #define QMI_WLANFW_CAP_REQ_V01				0x0024
297 #define QMI_WLANFW_CAP_RESP_V01				0x0024
298 #define QMI_WLANFW_DEVICE_INFO_REQ_V01			0x004C
299 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN	0
300 
301 enum qmi_wlanfw_pipedir_enum_v01 {
302 	QMI_WLFW_PIPEDIR_NONE_V01 = 0,
303 	QMI_WLFW_PIPEDIR_IN_V01 = 1,
304 	QMI_WLFW_PIPEDIR_OUT_V01 = 2,
305 	QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
306 };
307 
308 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
309 	__le32 pipe_num;
310 	__le32 pipe_dir;
311 	__le32 nentries;
312 	__le32 nbytes_max;
313 	__le32 flags;
314 };
315 
316 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
317 	__le32 service_id;
318 	__le32 pipe_dir;
319 	__le32 pipe_num;
320 };
321 
322 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
323 	u16 id;
324 	u16 offset;
325 };
326 
327 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 {
328 	u32 addr;
329 };
330 
331 struct qmi_wlanfw_memory_region_info_s_v01 {
332 	u64 region_addr;
333 	u32 size;
334 	u8 secure_flag;
335 };
336 
337 struct qmi_wlanfw_rf_chip_info_s_v01 {
338 	u32 chip_id;
339 	u32 chip_family;
340 };
341 
342 struct qmi_wlanfw_rf_board_info_s_v01 {
343 	u32 board_id;
344 };
345 
346 struct qmi_wlanfw_soc_info_s_v01 {
347 	u32 soc_id;
348 };
349 
350 struct qmi_wlanfw_fw_version_info_s_v01 {
351 	u32 fw_version;
352 	char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
353 };
354 
355 enum qmi_wlanfw_cal_temp_id_enum_v01 {
356 	QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
357 	QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
358 	QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
359 	QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
360 	QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
361 	QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
362 };
363 
364 struct qmi_wlanfw_cap_resp_msg_v01 {
365 	struct qmi_response_type_v01 resp;
366 	u8 chip_info_valid;
367 	struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
368 	u8 board_info_valid;
369 	struct qmi_wlanfw_rf_board_info_s_v01 board_info;
370 	u8 soc_info_valid;
371 	struct qmi_wlanfw_soc_info_s_v01 soc_info;
372 	u8 fw_version_info_valid;
373 	struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
374 	u8 fw_build_id_valid;
375 	char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
376 	u8 num_macs_valid;
377 	u8 num_macs;
378 	u8 voltage_mv_valid;
379 	u32 voltage_mv;
380 	u8 time_freq_hz_valid;
381 	u32 time_freq_hz;
382 	u8 otp_version_valid;
383 	u32 otp_version;
384 	u8 eeprom_read_timeout_valid;
385 	u32 eeprom_read_timeout;
386 };
387 
388 struct qmi_wlanfw_cap_req_msg_v01 {
389 	char placeholder;
390 };
391 
392 struct qmi_wlanfw_device_info_req_msg_v01 {
393 	char placeholder;
394 };
395 
396 struct qmi_wlanfw_device_info_resp_msg_v01 {
397 	struct qmi_response_type_v01 resp;
398 	u64 bar_addr;
399 	u32 bar_size;
400 	u8 bar_addr_valid;
401 	u8 bar_size_valid;
402 };
403 
404 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN	6182
405 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN	7
406 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01		0x0025
407 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01			0x0025
408 /* TODO: Need to check with MCL and FW team that data can be pointer and
409  * can be last element in structure
410  */
411 struct qmi_wlanfw_bdf_download_req_msg_v01 {
412 	u8 valid;
413 	u8 file_id_valid;
414 	enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
415 	u8 total_size_valid;
416 	u32 total_size;
417 	u8 seg_id_valid;
418 	u32 seg_id;
419 	u8 data_valid;
420 	u32 data_len;
421 	u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
422 	u8 end_valid;
423 	u8 end;
424 	u8 bdf_type_valid;
425 	u8 bdf_type;
426 
427 };
428 
429 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
430 	struct qmi_response_type_v01 resp;
431 };
432 
433 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN	18
434 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN	7
435 #define QMI_WLANFW_M3_INFO_RESP_V01		0x003C
436 #define QMI_WLANFW_M3_INFO_REQ_V01		0x003C
437 
438 struct qmi_wlanfw_m3_info_req_msg_v01 {
439 	u64 addr;
440 	u32 size;
441 };
442 
443 struct qmi_wlanfw_m3_info_resp_msg_v01 {
444 	struct qmi_response_type_v01 resp;
445 };
446 
447 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN	11
448 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN	7
449 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN		803
450 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN	7
451 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN		4
452 #define QMI_WLANFW_WLAN_MODE_REQ_V01			0x0022
453 #define QMI_WLANFW_WLAN_MODE_RESP_V01			0x0022
454 #define QMI_WLANFW_WLAN_CFG_REQ_V01			0x0023
455 #define QMI_WLANFW_WLAN_CFG_RESP_V01			0x0023
456 #define QMI_WLANFW_WLAN_INI_REQ_V01			0x002F
457 #define QMI_WLANFW_MAX_STR_LEN_V01			16
458 #define QMI_WLANFW_MAX_NUM_CE_V01			12
459 #define QMI_WLANFW_MAX_NUM_SVC_V01			24
460 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01		24
461 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01		36
462 
463 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
464 	u32 mode;
465 	u8 hw_debug_valid;
466 	u8 hw_debug;
467 };
468 
469 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
470 	struct qmi_response_type_v01 resp;
471 };
472 
473 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
474 	u8 host_version_valid;
475 	char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
476 	u8  tgt_cfg_valid;
477 	u32  tgt_cfg_len;
478 	struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
479 			tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
480 	u8  svc_cfg_valid;
481 	u32 svc_cfg_len;
482 	struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
483 			svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
484 	u8 shadow_reg_valid;
485 	u32 shadow_reg_len;
486 	struct qmi_wlanfw_shadow_reg_cfg_s_v01
487 		shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
488 	u8 shadow_reg_v2_valid;
489 	u32 shadow_reg_v2_len;
490 	struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01
491 		shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01];
492 };
493 
494 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
495 	struct qmi_response_type_v01 resp;
496 };
497 
498 struct qmi_wlanfw_wlan_ini_req_msg_v01 {
499 	/* Must be set to true if enablefwlog is being passed */
500 	u8 enablefwlog_valid;
501 	u8 enablefwlog;
502 };
503 
504 struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
505 	struct qmi_response_type_v01 resp;
506 };
507 
508 int ath11k_qmi_firmware_start(struct ath11k_base *ab,
509 			      u32 mode);
510 void ath11k_qmi_firmware_stop(struct ath11k_base *ab);
511 void ath11k_qmi_event_work(struct work_struct *work);
512 void ath11k_qmi_msg_recv_work(struct work_struct *work);
513 void ath11k_qmi_deinit_service(struct ath11k_base *ab);
514 int ath11k_qmi_init_service(struct ath11k_base *ab);
515 void ath11k_qmi_free_resource(struct ath11k_base *ab);
516 
517 #endif
518