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Searched refs:QCA956X_PLL_DDR_CONFIG1_REG (Results 1 – 2 of 2) sorted by relevance

/linux-5.19.10/arch/mips/ath79/
Dclock.c568 pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG); in qca956x_clocks_init()
/linux-5.19.10/arch/mips/include/asm/mach-ath79/
Dar71xx_regs.h435 #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c macro