1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_MMU_H
3 #define __KVM_X86_MMU_H
4
5 #include <linux/kvm_host.h>
6 #include "kvm_cache_regs.h"
7 #include "cpuid.h"
8
9 #define PT64_PT_BITS 9
10 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
11 #define PT32_PT_BITS 10
12 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
13
14 extern bool __read_mostly enable_mmio_caching;
15
16 #define PT_WRITABLE_SHIFT 1
17 #define PT_USER_SHIFT 2
18
19 #define PT_PRESENT_MASK (1ULL << 0)
20 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
21 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
22 #define PT_PWT_MASK (1ULL << 3)
23 #define PT_PCD_MASK (1ULL << 4)
24 #define PT_ACCESSED_SHIFT 5
25 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
26 #define PT_DIRTY_SHIFT 6
27 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
28 #define PT_PAGE_SIZE_SHIFT 7
29 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
30 #define PT_PAT_MASK (1ULL << 7)
31 #define PT_GLOBAL_MASK (1ULL << 8)
32 #define PT64_NX_SHIFT 63
33 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
34
35 #define PT_PAT_SHIFT 7
36 #define PT_DIR_PAT_SHIFT 12
37 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
38
39 #define PT32_DIR_PSE36_SIZE 4
40 #define PT32_DIR_PSE36_SHIFT 13
41 #define PT32_DIR_PSE36_MASK \
42 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
43
44 #define PT64_ROOT_5LEVEL 5
45 #define PT64_ROOT_4LEVEL 4
46 #define PT32_ROOT_LEVEL 2
47 #define PT32E_ROOT_LEVEL 3
48
49 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
50 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
51
52 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
53 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
54
rsvd_bits(int s,int e)55 static __always_inline u64 rsvd_bits(int s, int e)
56 {
57 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
58
59 if (__builtin_constant_p(e))
60 BUILD_BUG_ON(e > 63);
61 else
62 e &= 63;
63
64 if (e < s)
65 return 0;
66
67 return ((2ULL << (e - s)) - 1) << s;
68 }
69
70 /*
71 * The number of non-reserved physical address bits irrespective of features
72 * that repurpose legal bits, e.g. MKTME.
73 */
74 extern u8 __read_mostly shadow_phys_bits;
75
kvm_mmu_max_gfn(void)76 static inline gfn_t kvm_mmu_max_gfn(void)
77 {
78 /*
79 * Note that this uses the host MAXPHYADDR, not the guest's.
80 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
81 * assuming KVM is running on bare metal, guest accesses beyond
82 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
83 * (either EPT Violation/Misconfig or #NPF), and so KVM will never
84 * install a SPTE for such addresses. If KVM is running as a VM
85 * itself, on the other hand, it might see a MAXPHYADDR that is less
86 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
87 * disallows such SPTEs entirely and simplifies the TDP MMU.
88 */
89 int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52;
90
91 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
92 }
93
kvm_get_shadow_phys_bits(void)94 static inline u8 kvm_get_shadow_phys_bits(void)
95 {
96 /*
97 * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
98 * in CPU detection code, but the processor treats those reduced bits as
99 * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
100 * the physical address bits reported by CPUID.
101 */
102 if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
103 return cpuid_eax(0x80000008) & 0xff;
104
105 /*
106 * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
107 * custom CPUID. Proceed with whatever the kernel found since these features
108 * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
109 */
110 return boot_cpu_data.x86_phys_bits;
111 }
112
113 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
114 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
115 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
116
117 void kvm_init_mmu(struct kvm_vcpu *vcpu);
118 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
119 unsigned long cr4, u64 efer, gpa_t nested_cr3);
120 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
121 int huge_page_level, bool accessed_dirty,
122 gpa_t new_eptp);
123 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
124 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
125 u64 fault_address, char *insn, int insn_len);
126
127 int kvm_mmu_load(struct kvm_vcpu *vcpu);
128 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
129 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
130 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
131 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
132
kvm_mmu_reload(struct kvm_vcpu * vcpu)133 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
134 {
135 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
136 return 0;
137
138 return kvm_mmu_load(vcpu);
139 }
140
kvm_get_pcid(struct kvm_vcpu * vcpu,gpa_t cr3)141 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
142 {
143 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
144
145 return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
146 ? cr3 & X86_CR3_PCID_MASK
147 : 0;
148 }
149
kvm_get_active_pcid(struct kvm_vcpu * vcpu)150 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
151 {
152 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
153 }
154
kvm_mmu_load_pgd(struct kvm_vcpu * vcpu)155 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
156 {
157 u64 root_hpa = vcpu->arch.mmu->root.hpa;
158
159 if (!VALID_PAGE(root_hpa))
160 return;
161
162 static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
163 vcpu->arch.mmu->root_role.level);
164 }
165
166 /*
167 * Check if a given access (described through the I/D, W/R and U/S bits of a
168 * page fault error code pfec) causes a permission fault with the given PTE
169 * access rights (in ACC_* format).
170 *
171 * Return zero if the access does not fault; return the page fault error code
172 * if the access faults.
173 */
permission_fault(struct kvm_vcpu * vcpu,struct kvm_mmu * mmu,unsigned pte_access,unsigned pte_pkey,u64 access)174 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
175 unsigned pte_access, unsigned pte_pkey,
176 u64 access)
177 {
178 /* strip nested paging fault error codes */
179 unsigned int pfec = access;
180 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
181
182 /*
183 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
184 * For implicit supervisor accesses, SMAP cannot be overridden.
185 *
186 * SMAP works on supervisor accesses only, and not_smap can
187 * be set or not set when user access with neither has any bearing
188 * on the result.
189 *
190 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
191 * this bit will always be zero in pfec, but it will be one in index
192 * if SMAP checks are being disabled.
193 */
194 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
195 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
196 int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1;
197 bool fault = (mmu->permissions[index] >> pte_access) & 1;
198 u32 errcode = PFERR_PRESENT_MASK;
199
200 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
201 if (unlikely(mmu->pkru_mask)) {
202 u32 pkru_bits, offset;
203
204 /*
205 * PKRU defines 32 bits, there are 16 domains and 2
206 * attribute bits per domain in pkru. pte_pkey is the
207 * index of the protection domain, so pte_pkey * 2 is
208 * is the index of the first bit for the domain.
209 */
210 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
211
212 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
213 offset = (pfec & ~1) +
214 ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
215
216 pkru_bits &= mmu->pkru_mask >> offset;
217 errcode |= -pkru_bits & PFERR_PK_MASK;
218 fault |= (pkru_bits != 0);
219 }
220
221 return -(u32)fault & errcode;
222 }
223
224 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
225
226 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
227
228 int kvm_mmu_post_init_vm(struct kvm *kvm);
229 void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
230
kvm_shadow_root_allocated(struct kvm * kvm)231 static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
232 {
233 /*
234 * Read shadow_root_allocated before related pointers. Hence, threads
235 * reading shadow_root_allocated in any lock context are guaranteed to
236 * see the pointers. Pairs with smp_store_release in
237 * mmu_first_shadow_root_alloc.
238 */
239 return smp_load_acquire(&kvm->arch.shadow_root_allocated);
240 }
241
242 #ifdef CONFIG_X86_64
is_tdp_mmu_enabled(struct kvm * kvm)243 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; }
244 #else
is_tdp_mmu_enabled(struct kvm * kvm)245 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; }
246 #endif
247
kvm_memslots_have_rmaps(struct kvm * kvm)248 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
249 {
250 return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm);
251 }
252
gfn_to_index(gfn_t gfn,gfn_t base_gfn,int level)253 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
254 {
255 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
256 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
257 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
258 }
259
260 static inline unsigned long
__kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,unsigned long npages,int level)261 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
262 int level)
263 {
264 return gfn_to_index(slot->base_gfn + npages - 1,
265 slot->base_gfn, level) + 1;
266 }
267
268 static inline unsigned long
kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,int level)269 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
270 {
271 return __kvm_mmu_slot_lpages(slot, slot->npages, level);
272 }
273
kvm_update_page_stats(struct kvm * kvm,int level,int count)274 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
275 {
276 atomic64_add(count, &kvm->stat.pages[level - 1]);
277 }
278
279 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
280 struct x86_exception *exception);
281
kvm_translate_gpa(struct kvm_vcpu * vcpu,struct kvm_mmu * mmu,gpa_t gpa,u64 access,struct x86_exception * exception)282 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
283 struct kvm_mmu *mmu,
284 gpa_t gpa, u64 access,
285 struct x86_exception *exception)
286 {
287 if (mmu != &vcpu->arch.nested_mmu)
288 return gpa;
289 return translate_nested_gpa(vcpu, gpa, access, exception);
290 }
291 #endif
292