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Searched refs:PLL_WR_EN (Results 1 – 7 of 7) sorted by relevance

/linux-5.19.10/include/video/
Daty128.h240 #define PLL_WR_EN 0x00000080 macro
Dmach64.h136 #define PLL_WR_EN 0x02 macro
Dradeon.h511 #define PLL_WR_EN 0x00000080 macro
/linux-5.19.10/drivers/video/fbdev/aty/
Dradeon_pm.c1483 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1518 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1639 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1657 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
2277 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
2300 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
2430 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
2454 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
Dmach64_ct.c35 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); in aty_st_pll_ct()
38 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); in aty_st_pll_ct()
Daty128fb.c571 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); in _aty_st_pll()
Dradeon_base.c304 tmp = save & ~(0x3f | PLL_WR_EN); in radeon_pll_errata_after_data_slow()