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Searched refs:PIPECONF (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/gvt/
Ddisplay.c63 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
79 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
187 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= in emulate_monitor_status_change()
248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
249 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE; in emulate_monitor_status_change()
506 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
Dhandlers.c2264 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2265 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2266 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2267 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_drrs.c77 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in intel_drrs_set_refresh_rate_pipeconf()
84 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); in intel_drrs_set_refresh_rate_pipeconf()
Dintel_pch_display.c268 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_enable_pch_transcoder()
416 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ilk_pch_enable()
567 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
Dicl_dsi.c1049 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder()
1051 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder()
1054 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_enable_transcoder()
1317 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder()
1319 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder()
1322 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_disable_transcoder()
1753 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
Dintel_fdi.c947 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
1017 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
1046 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ilk_fdi_disable()
Dintel_display_power_well.c1035 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1037 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1051 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1052 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
Dintel_display.c434 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder), in intel_wait_for_pipe_off()
456 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); in assert_transcoder()
568 reg = PIPECONF(cpu_transcoder); in intel_enable_transcoder()
607 reg = PIPECONF(cpu_transcoder); in intel_disable_transcoder()
3055 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
3057 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
3193 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); in i9xx_set_pipeconf()
3194 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_set_pipeconf()
3353 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
3511 intel_de_write(dev_priv, PIPECONF(pipe), val); in ilk_set_pipeconf()
[all …]
Dintel_color.c513 val = intel_de_read(dev_priv, PIPECONF(pipe)); in i9xx_color_commit_arm()
516 intel_de_write(dev_priv, PIPECONF(pipe), val); in i9xx_color_commit_arm()
526 val = intel_de_read(dev_priv, PIPECONF(pipe)); in ilk_color_commit_arm()
529 intel_de_write(dev_priv, PIPECONF(pipe), val); in ilk_color_commit_arm()
Dintel_crt.c700 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
Dintel_dp.c3642 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_disable()
3650 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_disable()
3670 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); in intel_dp_autotest_phy_ddi_enable()
3678 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); in intel_dp_autotest_phy_ddi_enable()
Dvlv_dsi.c1059 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
/linux-5.19.10/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c115 MMIO_D(PIPECONF(PIPE_A)); in iterate_generic_mmio()
116 MMIO_D(PIPECONF(PIPE_B)); in iterate_generic_mmio()
117 MMIO_D(PIPECONF(PIPE_C)); in iterate_generic_mmio()
118 MMIO_D(PIPECONF(_PIPE_EDP)); in iterate_generic_mmio()
Di915_reg.h3819 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro