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Searched refs:PHY_REG (Results 1 – 11 of 11) sorted by relevance

/linux-5.19.10/drivers/net/ethernet/intel/e1000e/
Dich8lan.h110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
112 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
120 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
121 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
122 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
123 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
124 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
139 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
140 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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Dethtool.c1366 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1369 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1374 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1375 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1377 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1378 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1380 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1381 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1383 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_integrated_phy_loopback()
1384 e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400); in e1000_integrated_phy_loopback()
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Dich8lan.c1497 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1510 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1522 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
2282 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); in e1000_k1_gig_workaround_hv()
2288 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); in e1000_k1_gig_workaround_hv()
2467 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2582 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2583 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); in e1000_lv_jumbo_workaround_ich8lan()
2646 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2649 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
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Dregs.h243 #define I82579_DFT_CTRL PHY_REG(769, 20)
Dnetdev.c3087 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3090 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
/linux-5.19.10/drivers/phy/rockchip/
Dphy-rockchip-dphy-rx0.c110 #define PHY_REG(_offset, _width, _shift) \ macro
114 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
115 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
116 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
117 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
118 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
119 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
120 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
121 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
122 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
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Dphy-rockchip-inno-csidphy.c87 #define PHY_REG(_offset, _width, _shift) \ macro
91 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
92 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
93 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
97 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
98 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
99 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
103 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
Dphy-rockchip-inno-dsidphy.c37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
211 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
/linux-5.19.10/drivers/net/dsa/
Dlan9303_mdio.c18 #define PHY_REG(x) (((x) >> 1) & 0x1f) macro
27 mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); in lan9303_mdio_real_write()
45 return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); in lan9303_mdio_real_read()
/linux-5.19.10/drivers/net/ethernet/intel/e1000/
De1000_hw.h2915 #define PHY_REG(page, reg) \ macro
2919 PHY_REG(769, 17) /* Port General Configuration */
2921 PHY_REG(769, 25) /* Rate Adapter Control Register */
2924 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2926 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2928 PHY_REG(770, 18) /* KMRN Inband Control Register */
2930 PHY_REG(770, 19) /* KMRN Diagnostic register */
2933 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2936 PHY_REG(776, 18) /* Voltage regulator control register */
2941 PHY_REG(776, 19) /* IGP3 Capability Register */
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/linux-5.19.10/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dreg.h230 #define PHY_REG 0x02F3 macro